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ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
IRQ15, IRQ14, IRQ12鈥揑RQ9, IRQ7鈥揑RQ3, IRQ1
The JTAG pins described here are shared pin func-
tions. They are enabled by the JTAGEN signal.
JTAGEN
Interrupt Request
(Inputs; Rising Edge/Active High Trigger)
Interrupt Request input pins signal the internal 8259
compatible interrupt controller that an I/O device needs
servicing.
IRQ3 and IRQ6 are shared with PIRQ0 and PIRQ1.
IRQ0 is internally connected to the counter/timer, and
IRQ8 is internally connected to the real-time clock.
IRQ2 is used for cascading, and IRQ13 is reserved.
IRQ0, IRQ2, IRQ8, and IRQ13 are not available exter-
nally.
JTAG Enable (Input; Active High)
This pin enables the JTAG pin functions. When it is
High, the JTAG interface is enabled. When it is Low, the
JTAG pin functions are disabled and the pins are con-
figured to their default functions. See the Pin Designa-
tions, System Interface, and Miscellaneous Interface
tables for the JTAG pin default function descriptions.
For more information, see 鈥淪ystem Test and Debug鈥?on
page 74.
[TCK]
Note:
IRQ4, IRQ12, and IRQ15 are also available in
the Local Bus pin configuration.
LA23鈥揕A17
Test Clock (Input)
Test clock is a JTAG input clock that is used to access
the test access port when JTAGEN is active.
[TDI]
Latchable ISA Address Bus (Outputs)
These are the ISA latchable address signals. These
signals are valid early in the bus cycle so that external
peripherals may have time to decode the address and
return certain control feedback signals such as
MCS16.
LMEG
Test Data Input (Input)
Test data Input is the serial input stream for JTAG scan
input data when JTAGEN is active.
[TDO]
Address is in Low Meg (Output; Active Low)
This signal is active (Low) whenever the address for
the current cycle is in the first Mbyte of memory ad-
dress space (SA23 = SA22 = SA21 = SA20 = 0).
Test Data Output (3-State Output)
Test data Output is the serial output stream for JTAG
scan result data when JTAGEN is active.
[TMS]
Note:
LMEG
should not be used to generate SMEMR
or SMEMW. Instead, address lines SA23鈥揝A20 should
be decoded. For more information about
LMEG
, see the
脡lan
TM
SC300 and 脡lan
TM
SC310 Devices鈥?ISA Bus
Anomalies Application Note
, order #20747.
Test Mode Select (Input)
Test Mode Select is an input for controlling the Test Ac-
cess Port when JTAGEN is active.
RESET AND POWER
JTAG BOUNDARY SCAN INTERFACE
The 脡lanSC300 microcontroller provides an IEEE Std
1149.1-1990 (JTAG) compliant Standard Test Access
Port (TAP) and Boundary-Scan Architecture.
The boundary-scan test logic consists of a boundary
scan register and support logic that are accessed
through the TAP. The TAP provides a simple serial in-
terface that makes it possible to test the microcontroller
and system hardware in a production environment.
The TAP contains extensions that allow a hardware-
development system to control and observe the micro-
controller without interposing hardware between the
microcontroller and the system.
The TAP can be controlled via a bus master. The bus
master can be either automatic test equipment or a
component (PLD) that interfaces to the four-pin test
bus.
See the Voltage Partitioning section on page 95 for
more information about power.
AGND
Analog Ground pin
This pin is the ground for the analog circuitry and is bro-
ken out separately from the other GND pins making it
possible to filter AGND in a system that has a lot of
noise on the ground plane. In most applications, AGND
is tied directly to the ground plane with the other ground
pins on the microcontroller.
AVCC
3.3 V (only) Supply Pin
This supply pin provides power to the analog section of
the 脡lanSC300 microcontroller鈥檚 internal PLLs. Ex-
treme care should be taken that this supply voltage is
isolated properly to provide a clean, noise-free voltage
to the PLLs
44
脡lan鈩C300 Microcontroller Data Sheet

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