ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
Am386
SX/SXL/SXLV Data Sheet,
order #21020 and
the
Am386
DX/DXL Data Sheet,
order #21017.
Along with standard 386 architectural features, the
CPU core includes SMM. SMM and the other features
of the CPU are described in the
Am386DXLV and
Am386SXLV Microprocessors Technical Reference
Manual,
order #16944.
banks supporting up to 16 Mbyte of DRAM, utilizing in-
dustry standard modules. The 脡lanSC300 microcon-
troller shares the DRAM address lines MA0鈥揗A11 with
the upper system address lines SA12鈥揝A23 to reduce
pin count. This signal sharing is shown in Table 14.
Memory Controller
The 脡lanSC300 microcontroller memory controller is a
unified control unit that supports a high-performance,
16-bit data path to DRAM or SRAM. No external mem-
ory bus buffers are required and up to 16 Mbyte in two
16-bit banks can be supported. System memory must
always be configured as 16-bits wide. For more infor-
mation about the memory controller, see Chapter 2 of
the
脡lan
TM
SC300 Microcontroller Programmer鈥檚 Refer-
ence Manual
, order #18470. The System Block Dia-
gram, Figure 7 on page 64 of this manual, shows a
typical palm-top memory configuration.
The 脡lanSC300 microcontroller鈥檚 memory controller
supports an EMS-compatible Memory Mapping Sys-
tem (MMS) with 12 page registers. This facility can be
used to provide access to ROM-based software. MMS
is also used in the PCMCIA slot support. Shadow RAM
is also supported.
The Memory Controller supports one of three different
memory operating modes: SRAM, Page mode DRAM,
or Enhanced Page mode DRAM. Enhanced Page
mode increases DRAM access performance by effec-
tively doubling the DRAM page size in a two-bank
DRAM system by arranging the address lines such that
one page is spread across both DRAM banks. Both
DRAM modes use standard Fast Page mode DRAMs.
The memory controller operation is synchronous with
respect to the CPU. This ensures maximum perfor-
mance for all transfers to local memory. The clock
stretching implemented by the clock generation cir-
cuitry works to reduce synchronous logic power con-
sumption.
As shown in Table 13, the two DRAM operating modes
are defined by the MOD field in the Memory Configura-
tion Register, Index 66h, bit 0.
Table 14.
MA and SA Signal Pin Sharing
DRAM Memory Address
MA9鈥揗A0
MA10
MA11
System Address
SA23鈥揝A14
SA13
SA12
The 脡lanSC300 microcontroller also shares the DRAM
data bus with the system data bus on the D15鈥揇0 pins.
In a typical system, an SD bus is created with an exter-
nal x 16 bit buffer or level translator to isolate the
DRAM data bus from the rest of the system. Refer to
the Typical System Block Diagram, Figure 7 on page
64 of this data sheet. The DRAM configurations are
supported as shown in Table 11. The bank size infor-
mation in the table also applies when system memory
is configured as SRAM; however, SRAM uses a differ-
ent addressing scheme than DRAM and shares the
same address lines as the ISA bus. Chapter 2 in the
脡lan
TM
SC300 Microcontroller Programmer鈥檚 Refer-
ence Manual
, order #18470, contains more informa-
tion. Note that the configurations that use 512 Kbyte x
8 bit and 1 Mbyte x 16 bit DRAMs employ asymmetrical
addressing. Table 16 and Table 17 show the relation-
ship of the CPU address mapped to the DRAM mem-
ory.
Table 13.
0
1
DRAM Mode Selection
Function
Page mode
Enhanced Page mode
MOD0 (Index 66h, bit 0)
The 脡lanSC300 microcontroller defaults to a DRAM in-
terface. The SRAM mode is selected via bit 0 of the
Miscellaneous 6 Register Index 70h. The memory con-
troller provides for a direct connection of two 16-bit
46
脡lan鈩C300 Microcontroller Data Sheet

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