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ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
Table 17.
Index Index Index
B4h
66h
B1h
Bit
7
0
0
0
1
1
Bits
432
0 1 0
1
100
110
xxx
x x x
2
Bits
76
xx
xx
xx
01
11
DRAM Address Translation (Enhanced Page Mode)
DRAM Address
DRAM
Size Bank 0 Bank 1 RAS MA11MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
(Byte) (Byte) (Byte) CAS
2M
4M
16M
1M
4M
1M
2M
8M
512K
2M
1M
2M
8M
RAS
CAS
RAS
CAS
RAS
CAS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
A19 A18 A17 A16 A15 A14 A13 A12 A11 A20
鈥?/div>
A9 A8
A7 A6 A5
A4 A3 A2 A1
A19 A18 A17 A16 A15 A14 A13 A12 A21 A20
A10 A9 A8
A7 A6 A5 A4 A3 A2 A1
A22 A19 A18 A17 A16 A15 A14 A13 A23 A21 A20
A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
A18 A17 A16 A15 A14 A13 A12 A11 A19
A9 A8
A7 A6 A5 A4 A3 A2 A1
512K RAS
CAS
2M
RAS A20
CAS 鈥?/div>
A21 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
鈥?/div>
鈥?/div>
鈥?/div>
A8
A7 A6 A5 A4 A3 A2 A1
Notes:
1. Bit 4 of the Version Register, Index 64h must also be set for 2-Mbyte Enhanced Page mode. Also, bit 0 of Memory Configu-
ration 1 Register, Index 66h, must be a 1.
2. When 16-Mbit asymmetric DRAMs are used in a two-bank configuration (4 Mbyte), bits 1 and 0 of the Memory Configuration 1
Register, Index 66h, must be set for Enhanced Page mode only.
See Table 11 for a description of the physical organization of the DRAM devices supported.
Bit 0 of the Memory Configuration 1 Register, Index 66h must be set to enable Enhanced Page mode. Bit 1 of the Memory Con-
figuration 1 Register, Index 66h, must be set for DRAM. If set for SRAM, bits 0 and 1 control wait states.
SRAM
When using SRAM instead of DRAM for main memory,
up to 16 Mbyte can be accessed, the SRAM being or-
ganized as one or two banks. Each bank is 16 bits wide
and is provided with a low and high byte select.
An SRAM memory interface is selected by setting bit 0
of the Miscellaneous 6 Register, Index 70h. If this is
done, CAS1H, CAS1L, CAS0H, and CAS0L will have
their alternate function as SRAM chip select pins 3鈥?
(SRCS3鈥揝RCS0). Table 18 shows the key SRAM ac-
cess pins.
The MS2鈥揗S0 bits in the Memory Configuration Reg-
ister, Index 66, are also used to program the total
SRAM size. Bit 7 of the PCMCIA Card Reset Register,
Index B4h, must be cleared for SRAM configurations.
Table 19 contains information about SRAM wait state
logic, and Table 30 on page 71 contains SRAM inter-
face alternate pin information.
Table 18. SRAM Access Pins
Pin Name
SRCS0
SRCS1
SRCS2
SRCS3
SA23鈥揝A1
MWE
I/O
O
O
O
O
O
O
Function
SRAM Bank 0 Low Byte Select
SRAM Bank 0 High Byte Select
SRAM Bank 1 Low Byte Select
SRAM Bank 1 High Byte Select
Address (16 Mbyte maximum)
Write enable
See Table 15 on page 47 for bank size settings.
脡lan鈩C300 Microcontroller Data Sheet
49

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