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ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
PMC and PGP Pins
The 脡lanSC300 microcontroller supports five power
management control (PMC) pins and four programma-
ble general purpose (PGP) pins. The PMC pins can be
used to control the VCC rails of peripheral devices. The
PMC pins are related to the operating modes of the
脡lanSC300 microcontroller PMU. The PGP pins can be
used as general I/O chip selects for various uses.
The PMC4鈥揚MC0 pins are controlled by Configuration
Registers at Indexes 80h, 81h, ABh, and ACh. Each
pin can be programmed to be activated upon entry into
any of the PMU modes or driven directly by software.
PMC0 can be activated when the system is in High-
Speed PLL or Low-Speed PLL modes; PMC1 when the
system is in Doze mode; PMC2 when the system is in
Sleep mode; PMC3 and PMC4 when the system is in
Suspend mode; or just about any other combination.
These pins can then be used by the system designer to
shut off power to particular peripherals when the sys-
tem enters certain modes, just as internal clocks are
slowed or stopped in these modes. Upon the rising
edge of RESIN, PMC0, PMC1, PMC2, and PMC4 are
asserted Low and PMC3 is asserted High. Prior to this
edge, these signals are undefined.
The 脡lanSC300 microcontroller can be programmed to
reset a timer when an I/O access to a preset address
range is detected. If no I/O activity in that range occurs
before the timer expires, the 脡lanSC300 microcontrol-
ler can assert a PMC signal to turn off the device. When
S/W accesses that address range later, the 脡lanSC300
microprocessor can generate a System Management
Interrupt (SMI) to the processor, which then activates
an SMI handler routine. This routine then can deter-
mine the cause of the SMI and take appropriate action,
such as powering the I/O device back on.
The PGP3鈥揚GP0 pins are controlled by several config-
uration registers (70h, 74h, 89h, 91h, 94h, 95h, 9Ch,
A3h, and A4h) and their behavior is very flexible. PGP0
and PGP1 can be programmed as input or output.
PGP2 and PGP3 are dedicated outputs. PGP1 and
PGP3 can be gated with I/O reads, PGP0 and PGP2
can be gated with I/O writes, or each can act as an ad-
dress decode for a chip select.
The following paragraphs describe the 脡lanSC300 mi-
crocontroller in Micro Power Off mode. The following
are distinctive characteristics:
n
Minimum Power Consumption mode (approxi-
mately 25
碌A
typical, AVCC, and Core VCC com-
bined; AVCC and VCC are mandatory for Micro
Power Off mode).
n
Allows the system designer to utilize the internal
RTC and RTC RAM to maintain time, date, and
system configuration data while the other system
peripherals are powered off.
n
Provides the system designer with the option of
keeping the system DRAM powered and refreshed
while other system peripherals are powered off.
Self-refresh and CAS-before-RAS refresh DRAMs
are supported.
n
Minimal external logic required to properly control
power supplies and/or power switching.
n
No external buffering required to properly power
down system hardware.
The 脡lanSC300 microcontroller allows a system de-
signer to easily maintain the internal RTC and RTC
RAM and optionally, the DRAM interface, while the rest
of the system peripherals attached directly to the de-
vice are powered off. All 脡lanSC300 microcontroller
power pins associated with the I/O pins of external
powered-off peripherals must be powered down also.
This, in addition to internal termination, provides the re-
quired isolation to allow the external peripherals to be
powered off.
Automatically controlled internal I/O termination is pro-
vided to terminate the internal nodes of the 脡lanSC300
microcontroller properly when required.
The DRAM CAS-before-RAS, or self-refresh, can be
maintained by the 脡lanSC300 microcontroller in this
Micro Power State, if configured to do so, utilizing the
32-kHz oscillator. This clock continues to drive the RTC
and a portion of the core logic. See the
脡lan
TM
SC300
and 脡lan
TM
SC310 Microcontrollers Solution For Sys-
tems Using a Back-up Battery Application Note
, order
#20746 for more information about the 32-kHz oscilla-
tor and the RTC. The VMEM power plane (DRAM/
SRAM section power) must remain powered on if the
CAS-before-RAS refresh option is selected while in the
Micro Power state. The VMEM power plane must also
remain powered on if the self-refresh option is selected
and the specific DRAM device requires any of its con-
trol pins (i.e., WE, CAS, RAS, etc.) to remain inactive in
the Self-Refresh mode. If this is not required, it may be
possible for the system designer to remove power from
the VMEM pins when entering the Micro Power state,
even when the Self-Refresh mode DRAMs remain
powered on.
Micro Power Off Mode
Micro Power Off mode is the power management mode
that is used for battery backup.
Micro Power Off mode allows the system designer to
remove power from the VCC1, VSYS, VSYS2, VCC5,
and optionally, VMEM power inputs to the microcontrol-
ler. This allows the RTC timer and RAM contents to be
kept valid by using a battery back-up power source on
the VCC core and AVCC pins, which typically should
use only 25
碌A
in this mode.
脡lan鈩C300 Microcontroller Data Sheet
55

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