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ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
When entering Micro Power Off mode and the primary
power supply outputs are turned off, all of the
脡lanSC300 microcontroller鈥檚 powered-down I/O pins
are essentially tri-stated and the internal pull-ups are
removed because the VCCIO and VCC CLAMP of the
output driver have been removed, as shown in Figure
34 on page 101. This provides the ability to power off
external peripherals that are attached directly to the
脡lanSC300 microcontroller without concern of driving
current into the pins of the external powered-down de-
vice.
To assure that the 脡lanSC300 microcontroller does not
draw excessive power while in this state, internal pull-
down resistors will be enabled. Enabling these resis-
tors keeps the input buffers from floating (see Figure 4).
The 脡lanSC300 microcontroller samples the two reset
inputs (RESIN and IORESET) to logically determine
what state the power pins are in; and, in turn, controls
the internal pull-down resistors. Note that in Micro
Power Off mode, the IORESET input should be termi-
nated with a pull-down resistor if not driven Low by an
external device (see Table 24 on page 59 for informa-
tion about internal I/O pull-down states).
Micro Power Off DRAM Refresh
Refresh can be either enabled or disabled during Micro
Power Off mode, and the VMEM power can be option-
ally removed, provided that either the memory is also
powered off or all DRAM interface signals are kept at
0 V. See the timing diagrams in Figure 34 and Figure
35 on page 101 for more information.
The system designer has the option to keep the system
DRAM powered up and refreshed while the 脡lanSC300
microcontroller is in the micro power state. A configura-
tion bit, the Micro Power Refresh Enabled bit, exists in
the PMU section of the core logic to realize this feature.
This is bit 2 of the Miscellaneous 3 Register at Index
BAh. If this bit is cleared (default), the core logic asso-
ciated with the DRAM refresh will be disabled when the
脡lanSC300 microcontroller is in the Micro Power state.
If the bit is set, the core logic associated with the DRAM
refresh will be enabled and functional while the
脡lanSC300 microcontroller is in its Micro Power state.
Core Logic
I/O Driver
VCCIO
VCC CLAMP
Pins
Pull-Up
Resistor
Data Out
To Core Logic
VCC Core
Output Enable
Level
Translator and
Pre-Driver
IN
BUF
I/O
PAD
Level
Translator and
Pre-Driver
Force Term
Pull-Down
Resistor
Where:
VCCIO = VCC5, VMEM, VSYS, VSYS2, AVCC, or VCC1
VCC CLAMP = VCC5, VMEM, or AVCC
Figure 4.
脡lanSC300 Microcontroller I/O Structure
脡lan鈩C300 Microcontroller Data Sheet
57

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