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ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
Core Peripheral Controllers
The 脡lanSC300 microcontroller includes all the stan-
dard peripheral controllers that make up a PC/AT sys-
tem, including interrupt controller, DMA controller,
counter/timer, and ISA bus controller. For more infor-
mation, see Chapter 4 of the
脡lan
TM
SC300 Microcon-
troller Programmer鈥檚 Reference Manual
, order #18470.
Interrupt Controller
The 脡lanSC300 microcontroller interrupt controller is
functionally compatible with the standard cascaded
8259A controller pair as implemented in the PC/AT.
The interrupt controller block accepts requests from
peripherals, resolves priority on pending interrupts and
interrupts in service, issues an interrupt request to the
processor, and provides the interrupt vector to the
processor.
The two devices are internally connected and must be
programmed to operate in Cascade mode for operation
of all 15 interrupt channels. Interrupt controller 1 occu-
pies I/O addresses 020h鈥?21h and is configured for
master operation in Cascade mode. Interrupt controller
2 occupies I/O addresses 0A0h鈥?A1h and is config-
ured for slave operation. Channel 2 (IRQ2) of interrupt
controller 1 is used for cascading and is not available
externally.
The output of Timer 0 in the counter/timer section is
connected to Channel 0 (IRQ0) of Interrupt controller 1.
IRQ0 can be programmed to generate an SMI. See
Chapter 1 of the
脡lan
TM
SC300 Microcontroller Pro-
grammer鈥檚 Reference Manual
, order #18470. Interrupt
request from the Real-Time Clock is connected to
Channel 0 (IRQ8) of Interrupt Controller 2. IRQ13 is re-
served for the coprocessor in a PC/AT system and is
unavailable on the 脡lanSC300 microcontroller. The
other interrupts are available to external peripherals as
in the PC/AT architecture via the IRQ15, IRQ14,
IRQ12鈥揑RQ9, IRQ7鈥揑RQ3, and IRQ1 inputs. Other
sources of interrupts are SMI/NMI and the PIRQ1鈥?/div>
PIRQ0 inputs.
The 脡lanSC300 microcontroller interrupt controller has
programmable sources for interrupts. These program-
mable sources are controlled by the configuration reg-
isters. For more information, see Chapter 5 of the
脡lan
TM
SC300 Microcontroller Programmer鈥檚 Refer-
ence Manual
, order #18470.
The Interrupt controller provides interrupt information
to the 脡lanSC300 microcontroller power management
unit to allow the monitoring of system activity. The
脡lanSC300 microcontroller power management unit
can then use the interrupt activity to control the Power
Management mode of the 脡lanSC300 microcontroller.
For more information, see Chapter 1 of the
脡lan
TM
SC300 Microcontroller Programmer鈥檚 Refer-
ence Manual
, order #18470.
DMA Controller
The 脡lanSC300 microcontroller DMA controller is func-
tionally compatible with the standard cascaded 8237
controller pair. Channels 0, 1, 2, and 3 are externally
available 8 bit channels. DMA Channel 4 is the cas-
cade channel. Channels 5, 6, and 7 are externally
available as 16 bit channels.
All the DMA channels are masked off on hardware
reset or when writing the DMA master reset register.
Note:
To enable the master to percolate the request to
the CPU, you must also unmask the cascade channel
(0) on the master.
The 脡lanSC300 microcontroller supports the power-
saving clock stop feature that causes the clock to the
DMA controller to stop except when actually needed to
perform a DMA transfer. For more information about
clock states and programmable clock frequencies, see
Table 23 on page 54.
The 脡lanSC300 microcontroller supports Single,
Block, and Demand transfer modes; however, soft-
ware-initiated DMA requests, Cascade mode for addi-
tional external DMA controllers, and Verify mode are
not supported.
For more information about the DMA controller, see the
脡lan
TM
SC300 Microcontroller Programmer鈥檚 Refer-
ence Manual
, order #18470.
Counter/Timer
The 脡lanSC300 microcontroller鈥檚 counter/timer is func-
tionally compatible with the 8254 device. A 3-channel,
general-purpose, 8254 compatible, 16-bit counter/
timer is integrated into the 脡lanSC300 microcontroller.
It can be programmed to count in binary or in Binary
Coded Decimal (BCD). Each counter operates inde-
pendently of the other two and can be programmed for
operation as a timer or a counter. All three are con-
trolled from a common set of control logic, which pro-
vides controls to load, read, configure, and control
each counter.
All of the 8254 compatible counter/timer channels are
driven from a common clock that is internally generated
from the LS_PLL 1.1892-MHz output. The output of
Counter 0 is connected to IRQ0.
Additional Peripheral Controllers
The 脡lanSC300 microcontroller also integrates three
other peripheral controllers commonly found in PCs,
but not considered part of the 鈥渃ore peripherals,鈥?/div>
namely a serial port or a Universal Asynchronous Re-
ceiver Transmitter (UART), a real-time clock (RTC),
60
脡lan鈩C300 Microcontroller Data Sheet

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