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ELANSC300-33KI Datasheet

  • ELANSC300-33KI

  • Highly Integrated, Low-Power, 32-Bit Microcontroller

  • 1344.13KB

  • 139页

  • AMD

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P R E L I M I N A R Y
and a parallel port. See Chapter 4 of the
脡lan
TM
SC300
Microcontroller Programmer鈥檚 Reference Manual
,
order #18470.
16450 UART
The 脡lanSC300 microcontroller chip includes a UART,
providing 脡lanSC300 microcontroller systems with a
serial port. This serial controller is fully compatible with
the industry-standard 16450. In handheld systems, this
port can connect to the pen input device or to a modem.
Real-Time Clock
The 脡lanSC300 microcontroller contains a fully
146818A-compatible real-time clock (RTC) imple-
mented in a PC/AT-compatible fashion. The RTC
drives its interrupt to power-management logic.
The RTC block in the 脡lanSC300 microcontroller con-
sists of a time-of-day clock with alarm and 100-year
calendar. The clock/calendar can be represented in bi-
nary or BCD. It has a programmable periodic interrupt,
and 114 bytes of general purpose static RAM (an ex-
tension of the 146818A standard, see the program-
mer鈥檚 reference manual for more details).
Parallel Port
The 脡lanSC300 microcontroller parallel port is func-
tionally compatible with the PS/2 parallel port. The
脡lanSC300 microcontroller parallel port interface pro-
vides the parallel port control outputs and status inputs,
and also the control signals for the parallel port data
buffers. The parallel port data path is external to the
脡lanSC300 microcontroller. This interface can be con-
figured to operate in either a Unidirectional (normal)
mode or Bidirectional (EPP) mode.
The unidirectional parallel port requires only one exter-
nal component, the parallel port data latch. This latch is
used to latch the data from the data bus and drive the
data onto the parallel port data bus, as shown in
Figure 5.
When the 脡lanSC300 microcontroller parallel port is
configured for Bidirectional mode operation, the
PPDWE pin is reconfigured via firmware to function as
the Parallel Port Data Register address decode
(PPDCS). The PPOEN output from the 脡lanSC300 mi-
crocontroller is controlled via the Parallel Port Control
Register Bit 5. This signal is then used to control the
output enable of the external parallel port data latch. By
setting this bit, the parallel port data latch is disabled,
and then data can be transferred from an external par-
allel port device into the 脡lanSC300 microcontroller
through an external 244 type buffer. A typical bidirec-
tional Parallel Port Data Bus implementation is shown
in Figure 6.
If the VCC5 supply pins are connected to a 5-V power
supply, then the Parallel Port control signals will be
driven by 5-V outputs and can be connected directly to
the parallel port connector. If VCC5 is connected to 3.3
V, the parallel port control signals should be translated
to 5 V.
The 脡lanSC300 CPU also supports Enhanced Parallel
Port (EPP) mode. The EPP mode pins are defined in
Table 25.
Note:
If PCMCIA write enable (
PCMCWE
) and PCM-
CIA output enable (
PCMCOE
) are used, the parallel port
signals INIT and SLCTIN are not available.
Table 25. Parallel Port EPP Mode Pin Definition
Normal
Mode
STRB
EPP
Mode
WRITE
Description
EPP write signal. This signal is
driven active during writes to
the EPP data or address regis-
ter.
EPP data strobe. This signal is
driven active during reads or
writes to the EPP data register.
EPP address strobe. This sig-
nal is driven active during
reads or writes to the EPP ad-
dress register.
EPP interrupt. This signal is an
input used by the EPP device
to request service.
EPP wait. This signal is used to
add wait states to the current
cycle. It is similar to the ISA
IOCHRDY signal.
AFDT
DSTRB
SLCTIN
374 Octal D Flip Flop
SD7鈥揝D0
D
Q
Parallel Port
Data Bus
ACK
ASTRB
INTR
BUSY
PPDWE
CLK
OE
WAIT
Figure 5.
脡lanSC300 Microcontroller
Unidirectional Parallel Port Data Bus
Implementation
In Normal mode, the outputs shown in Table 25 func-
tion as open-collector or open-drain outputs. In EPP
mode, these outputs must function as standard CMOS
outputs that are driven High and Low. Figure 6 shows
the design that should be used to support EPP mode.
脡lan鈩C300 Microcontroller Data Sheet
61

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