P R E L I M I N A R Y
373 Octal D Transparent Latch
SD7鈥揝D0
D
Q
Parallel Port
Data Bus
EN
PPOEN
OE
PPDCS
IOW
244 type buffer
Y
A
ENB
IOR
Figure 6. The 脡lanSC300 CPU Bidirectional Parallel Port and EPP Implementation
Parallel Port Anomalies
General
The 脡lanSC300 microcontroller parallel port can be
physically mapped to three different I/O locations or
can be completely disabled. These I/O locations are
3B(x)h, 37(x)h, and 27(x)h. Typically the system BIOS
or a software driver sets up the port at system boot
time. Generally, LPT1 is set up by software to be asso-
ciated with IRQ7, and LPT2 (and LPT3 if desired) is set
up to be associated with IRQ5. In the 脡lanSC300 mi-
crocontroller, the parallel port is always associated with
IRQ7. This cannot be changed regardless of the
I/O location to which the parallel port is mapped.
Local Bus or Maximum ISA Configuration
When the 脡lanSC300 microcontroller is configured for
some bus mode other than the internal CGA controller
option, the system BIOS should disable the internal
video controller at boot time. This is done by setting bit
5 of the Screen Control Register 2, Index 19h in the
CGA Index address space.
Control Register 1, Index 20h in the CGA Index ad-
dress space, controls the parallel port mapping. When
the internal CGA controller is disabled, Control Regis-
ter 1 cannot be accessed until the part is reset. There-
fore, once the internal CGA controller has been
disabled, the parallel port cannot be remapped. This
can cause the system boot sequence to require modi-
fication such that the parallel port is set up prior to the
disabling of the internal video controller. In addition,
any software driver or setup utility which was loaded
after the internal video controller was disabled would
not have the ability to remap the parallel port location if
it was required. For more information about parallel
ports, see Chapter 4 of the
脡lan
TM
SC300 Microcontrol-
ler Programmer鈥檚 Reference Manual
, order #18470.
PC/AT Support Features
The 脡lanSC300 microcontroller provides all of the sup-
port functions found in the original PC/AT. These in-
clude the Port B status and control bits, speaker
control, extensions for fast reset, and A20 gate control.
(Fast CPU reset and fast A20 gate functions are con-
trolled by either the Miscellaneous 1 Register, Index
6Fh, or port 92h). For more information, see Chapter 4
of the
脡lan
TM
SC300 Microcontroller Programmer鈥檚
Reference Manual
, order #18470.
The 脡lanSC300 microcontroller also includes support
for port B, and a miscellaneous PC/AT register that al-
lows direct programming of the speaker via the SPK
line. In addition, the 脡lanSC300 microcontroller also
generates a chip select and clock source for an exter-
nal, standard 8042 keyboard controller or the PC/XT
keyboard feature. For more information, see Appendix
B of the
脡lan
TM
SC300 Microcontroller Programmer鈥檚
Reference Manual
, order #18470.
Port B and NMI Control
Port B is a PC/AT-standard miscellaneous feature con-
trol register that is located at I/O address 061h. The
62
脡lan鈩C300 Microcontroller Data Sheet