SNJ54LV595AJ Datasheet

IC型号：
SNJ54LV595AJ
PDF描述：
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
文件大小：
489.81KB
PDF页数：
20页
芯片厂家：
TI

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SN54LV595A, SN74LV595A

8 BIT SHIFT REGISTERS

WITH 3 STATE OUTPUT REGISTERS

SCLS414N 鈭?APRIL 1998 鈭?REVISED APRIL 2005

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LV595A

PARAMETER

TEST CONDITIONS

IOH = 鈭?0

碌A

IOH = 鈭? mA

VOH

QH鈥?/div>

QA鈭扱H

QH鈥?/div>

QA鈭扱H

IOH = 鈭? mA

IOH = 鈭?2 mA

IOH = 鈭?6 mA

IOL = 50

碌A

IOL = 2 mA

VOL

QH鈥?/div>

QA鈭扱H

QH鈥?/div>

QA鈭扱H

IOZ

ICC

Ioff

IOL = 6 mA

IOL = 8 mA

IOL = 12 mA

IOL = 16 mA

VI = 5.5 V or GND

VO = VCC or GND,

VI = VCC or GND,

VI or VO = 0 to 5.5 V

VI = VCC or GND

QA鈭扱H

IO = 0

VCC

2 V to 5.5 V

2.3 V

4.5 V

2 V to 5.5 V

2.3 V

4.5 V

0 to 5.5 V

5.5 V

3.3 V

3.5

MIN

VCC鈭?.1

2.48

3.8

0.1

0.4

0.44

0.55

卤1

卤5

3.5

TYP

MAX

SN74LV595A

MIN

VCC鈭?.1

2.48

3.8

0.1

0.4

0.44

0.55

卤1

卤5

碌A

TYP

MAX

UNIT

timing requirements over recommended operating free-air temperature range, V

= 2.5 V

卤

0.2 V

(unless otherwise noted) (see Figure 1)

TA = 25掳C

MIN

MAX

SRCLK high or low

Pulse duration

RCLK high or low

SRCLR low

SER before SRCLK鈫?/div>

SRCLK鈫?before RCLK鈫戔€?/div>

tsu

Setup time

SRCLR low before RCLK鈫?/div>

SRCLR high (inactive) before SRCLK鈫?/div>

5.5

8.5

SN54LV595A

MIN

7.5

6.5

5.5

9.5

MAX

SN74LV595A

MIN

7.5

6.5

5.5

9.5

MAX

UNIT

Hold time

SER after SRCLK鈫?/div>

1.5

鈥?This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

POST OFFICE BOX 655303

鈥?/div>

DALLAS, TEXAS 75265

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