CS98200
Next Generation DVD Processor
2.2.4
SDRAM Interface
CS98200 interfaces with either SDRAM or SGRAM for high data bandwidth transfer.
Figure 8
shows
the refresh cycle performed by CS98200.
Symbol
t
Description
Output Delay from M_CKO active edge
M_CKO Period
M_D[31:0] delay from M_CKO
M_D[31:0] setup to M_CKO
M_D[31:0] hold time after M_CKO
3
8
Min
Typ
9
Max
Unit
ns
ns
mco
t
mper
t
t
mdow
msur
9
ns
ns
ns
t
mhr
2.5
Table 2. SDRAM Interface Characteristics
M_CKO
M_A[10:0]
M_BS0_N, M_BS1_N
M_RAS_N
M_CAS_N
M_W E_N
M_D[31:0]
M_DQM_[3:0]
M_AP
Figure 8. SDRAM Refresh Transaction
M_C KO
M_A_[10:0]
M_C KE
M_R AS _N
M_C AS _N
M_W E_N
M_D [31:0]
M_D Q M[3:0]
F
D0
D1
D2
D3
0
D4
D5
D6
D7
F
R0
C0
C1
C2
C3
C4
C5
C6
C7
Figure 9. SDRAM Burst Write Transaction
16
铮?/div>
Copyright 2002 Cirrus Logic (All Rights Reserved)
DS581PP2
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