CS98200
Next Generation DVD Processor
Universal Asynchronous
Receiver/Transmitters (UARTs)
The UART performs serial-to-parallel conver-
sion on data characters received from a periph-
eral device and parallel-to-serial conversion on
data characters received from the host proces-
sor.
Figure 22
shows RXD and TXD data trans-
fers over the UART interface.
The CS98200 has 2 UART interfaces based on a
NS16550-compatible design, which incorpo-
rates 16-byte transmit and receive FIFOs to en-
hance performance and throughput. As with
the 16650, it can operate in both FIFO-mode
(16550) or in the original non-FIFO mode
(16450). The main registers are identical in
structure to the NS16550, but some unused bits
have been enabled for added functionality.
The standard features are:
鈥?Compatible with 16450 UART
鈥?16-byte transmit and receive FIFOs reduce
number of interrupts presented to CPU
鈥?Generates and detects standard asynchronous
communication bits (start, stop and parity) to
and from serial data
鈥?Independently controlled transmit, receive, line
status and data set interrupts
鈥?Programmable baud rate generator (16 bit
divisor)
5.12
鈥?Modem control interface (CTS, RTS, DSR, DTR,
RI and DCD)
鈥?Fully programmable serial-interface
characteristics:
鈥?5, 6, 7 or 8 bit characters
鈥?Even, odd or no-parity bit
generation/detection
鈥?1, 1锟?frac12;, or 2 stop bit generation
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
False start bit detection
Complete status reporting capabilities
Line break generation and detection
Internal loopback diagnostic mode
Programmable trigger levels for FIFOs
Selectable DMA signaling mode
Prioritized interrupts
Transmitter and receiver FIFO time-out
interrupts
Additional optimizations:
鈥?Byte enable register allows transfer of up to 4
bytes in a single register write (only in FIFO
mode).
鈥?External loopback diagnostic mode
鈥?Separate baud clock input available
鈥?Additional receiver error information
Note: If using separate baud clock, it must be less
than 锟?frac12; frequency of the system clock,
otherwise, you must use the system clock.
RXD
S ta rt
D a ta B its (5 ~ 8 )
P a rity
S to p
TXD
S ta rt
D a ta B its (5 ~ 8 )
P a rity
S to p
S ta rt
Figure 22. UART Data Transfer
34
铮?/div>
Copyright 2002 Cirrus Logic (All Rights Reserved)
DS581PP2
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