鈥?/div>
1
Q
0
1
8
V
CC
DFN8
MN SUFFIX
CASE 506AA
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb鈭扚ree Package
Q
0
2
7
D
Q
1
3
6
D
(Note: Microdot may be in either location)
Q
1
4
5
V
EE
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Figure 1. Logic Diagram and Pinout Assignment
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
December, 2006
鈭?/div>
Rev. 8
1
Publication Order Number:
MC100LVEL11/D
3Z M
G
G
4
330 ps Propagation Delay
5 ps Skew Between Outputs
High Bandwidth Output Transitions
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.0
V to
鈭?.8
V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at V
EE
Pb鈭扚ree Packages are Available
8
KV11
ALYWG
G
1
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