3-Phase Synchronous PWM Controller IC Provides an
Integrated Solution for Intel VRM 9.0 Design Guidelines
Odile Ronat
International Rectifier
The fundamental reason for the rapid change and
growth in information technology power
requirements is the increase in volume of data
processed, stored, transmitted, and displayed. As
a result, power requirements have grown very
rapidly. To control the increase in power
dissipation, operating voltages have been
reduced. Power scales as the square of the
voltage: cut the voltage in half, and the power
dissipation is reduced to one fourth. As circuit
output voltages approach the one-volt mark,
operating currents are increasing exponentially.
Today, feeding this much 鈥渦ltraclean鈥?current at
these low voltages with tremendous transient
response capability is the key technology driver
of power management for IT.
CPUs used in servers, advance desktop
computers and motherboards such as the Intel
Pentium鈩?4 or Xeon鈩?or AMD K7鈩?typically
require currents up to 60A at output voltages
around 1V, with transient response in the order
of 50A/us. Designers prefer a multiphase DC-
DC converter topology to address the higher
current requirements
response problem,
and
faster
transient
This article will discuss the specific
requirements for DC-DC converters required to
power today鈥檚 GHz class CPUs, the benefits of
the multiphase topology, and an example of
implementation of Intel VRM 9.0 using an
integrated 3-phase synchronous PWM controller
IC.
An Overview of Intel VRM 9.0 Design
Guidelines
With today鈥檚 microprocessor voltage below 2V,
they cannot be powered directly out of the
conventional silver box that typically provides
5V and 12V. Located in proximity to the CPU,
the voltage regulator module (VRM) delivers
regulated, stepped down voltage to the CPU.
The Intel VRM 9.0 definition is specifically
intended to meet the needs of systems based on
the Intel 庐 Xeon鈩?and Pentium 庐 4 processors.
Table 1 provides a summary of the output
requirements for VRM 9.0.
Table 1
- Summary of the VRM 9.0 output requirements (Source: Intel VRM9.0 DC-DC converter design guidelines.
Other requirements include VID voltage
identification and Power Good feedback. The
VRM must accept five lines to set the nominal
maximum voltage. Five processor package pins
will have a high-low pattern corresponding to
the voltage required by the individual processor.
The VRM should provide an open collector
1
1
2
3
4
5
