ST 486 DX ASIC CORE
Fully Static 3.3V 486 DX/DX2/DX4 ASIC CORE
PRELIMINARY DATA
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Fully Static 486 compatible core able to
operate from D.C to 120MHz
Manufactured in a 0.35 micron five layer
metal HCMOS process
8K byte unified instruction and data cache
with write back capability
Parallel processing integral floating point unit,
with automatic power down mode
Low Power system management modes
Cell libraries for 2.2V and 3.3V supply with
5 V I/O interface capability
2 - input NAND delay of 0.160 ns (typ) with
fanout = 2.
Broad I/O functionality including LVCMOS,
LVTTL, GTL, PECL, and LVDS.
High drive I/O; capability of sinking up to 48
mA with slew rate control, current spike sup-
pression and impedance matching.
Generators to support SPRAM, DPRAM,
ROM and many other embedded functions.
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Fully independent power and ground configu-
rations for inputs, core and outputs.
Programmable I/O ring capability up to 1000
pads.
Output buffers capable of driving ISA, EISA,
PCI, MCA, and SCSI interface levels.
Active pull up and pull down devices.
Buskeeper I/O functions.
Oscillators for wide frequency spectrum.
Broad range of 400 SSI cells.
Design For Test includes LSSD macro library
option and IEEE 1149.1 JTAG Boundary
Scan architecture built in.
Cadence based design system with inter-
faces from multiple workstations.
Broad ceramic and plastic package range.
Latchup trigger current > +/- 500 mA.
ESD protection > +/- 4000 volts.
Figure 1. Example 486 DX Core ASIC
S e a o f G at e s
S t a n d ar d C e l ls
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SV G A
C H IP S E T / P C I
ID E / IS A
486
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ROM
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DX CORE
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C u s t o m I/ O
e .g R A M D A C
October 1995
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