鈥?/div>
Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at 125掳C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
54AC11175 . . . J PACKAGE
74AC11175 . . . DW or N PACKAGE
(TOP VIEW)
t
1Q
2Q
2Q
GND
GND
GND
GND
3Q
3Q
4Q
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1Q
CLR
1D
2D
V
CC
V
CC
3D
4D
CLK
4Q
description
These positive-edge-triggered flipflops implement
D-type flip-flop logic with a direct clear input.
Information at the D inputs that meets the setup
time requirements is transferred to the outputs on
the positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock input is at
either the high or low level, the D input signal has
no effect at the output.
The 54AC11175 is characterized for operation
over the full military temperature range of 鈥?55掳C
to 125掳C. The 74AC11175 is characterized for
operation from 鈥?40掳C to 85掳C.
54AC11014 . . . FK PACKAGE
(TOP VIEW)
CLR
1Q
1Q
2Q
2Q
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1D
2D
V
CC
V
CC
3D
4D
CLK
4Q
4Q
3Q
OUTPUTS
D
X
H
L
X
Q
L
H
L
Q0
Q
H
L
H
Q0
Copyright
漏
1993, Texas Instruments Incorporated
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
L
H
H
H
CLK
X
鈫?/div>
鈫?/div>
L
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
GND
GND
CND
GND
3Q
2鈥?
1
2
3
4
5
6
7
