74ACT11032
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCAS008C 鈥?JULY 1987 鈥?REVISED APRIL 1996
D
D
D
D
D
Inputs Are TTL-Voltage Compatible
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at 125掳C
Package Options Include Plastic
Small-Outline Packages (D), Plastic Shrink
Small-Outline Packages (DB), Plastic Thin
Shrink Small-Outline Packages (PW), and
Standard Plastic 300-mil DIPs (N)
D, DB, N, OR PW PACKAGE
(TOP VIEW)
1A
1Y
2Y
GND
GND
3Y
4Y
4B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
2A
2B
V
CC
V
CC
3A
3B
4A
description
This device contains four independent 2-input OR gates. It performs the Boolean function Y = A + B or
Y
+
A
鈥?/div>
B in positive logic.
The 74ACT11032 is characterized for operation from 鈥?0掳C to 85掳C.
FUNCTION TABLE
(each gate)
INPUTS
A
H
X
L
B
X
H
L
OUTPUT
Y
H
H
L
logic symbol
鈥?/div>
1A
1B
2A
2B
3A
3B
4A
4B
1
16
15
14
11
10
9
8
7
4Y
6
3Y
3
2Y
logic diagram (positive logic)
鈮?/div>
2
1A
1Y
1B
2A
2B
3A
3B
4A
4B
4Y
3Y
2Y
1Y
鈥?This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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