74LCX10 Low Voltage Triple 3-Input NAND Gate with 5V Tolerant Inputs
June 2000
Revised February 2005
74LCX10
Low Voltage Triple 3-Input NAND Gate
with 5V Tolerant Inputs
General Description
The LCX10 contains three 3-input NAND gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V sys-
tems to 3V systems.
The 74LCX10 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs
s
2.3V鈥?.6V V
CC
specifications provided
s
4.9 ns t
PD
max (V
CC
3.3V), 10
P
A I
CC
max
3.0V)
s
Power down high impedance inputs and outputs
s
r
24 mA output drive (V
CC
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Ordering Code:
Order Number
74LCX10M
74LCX10SJ
74LCX10MTC
Package Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
n
, B
n
, C
n
O
n
Description
Inputs
Outputs
Truth Table
O
n
A
n
X
X
L
H
H HIGH Voltage Level
L LOW Voltage Level
A
n
B
n
C
n
C
n
L
X
X
H
Immaterial
B
n
X
L
X
H
X
O
n
H
H
H
L
漏 2005 Fairchild Semiconductor Corporation
DS500453
www.fairchildsemi.com