74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
October 1995
Revised March 2001
74LCX841
Low Voltage 10-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs
General Description
The LCX841 consists of ten latches with 3-STATE outputs
for bus organized system applications. The device is
designed for low voltage (2.5V or 3.3V) V
CC
applications
with capability of interfacing to a 5V signal environment.
The LCX841 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V
鈭?/div>
3.6V V
CC
specifications provided
s
8.0 ns t
PD
max (V
CC
=
3.3V), 10
碌
A I
CC
max
s
Power-down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
卤
24 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human Body Model
>
2000V
Machine Model
>
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX841WM
74LCX841MSA
74LCX841MTC
Package Number
M24B
MSA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
漏 2001 Fairchild Semiconductor Corporation
DS012575
www.fairchildsemi.com
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