74VHC86 Quad 2-Input Exclusive-OR Gate
November 1992
Revised February 2005
74VHC86
Quad 2-Input Exclusive-OR Gate
General Description
The VHC86 is an advanced high speed CMOS Quad
Exclusive OR Gate fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and on two supply systems such as battery back up. This
circuit prevents device destruction due to mismatched sup-
ply and input voltages.
Features
s
High Speed: t
PD
4.8 ns (typ) at V
CC
V
NIL
5V
25
q
C
s
Low Power Dissipation: I
CC
s
High Noise Immunity: V
NIH
s
Low Noise: V
OLP
2
P
A (Max.) @ T
A
28% V
CC
(Min.)
s
Power down protection is provided on all inputs
0.8V (Max.)
s
Pin and Function Compatible with 74HC86
Ordering Code:
Order Number
74VHC86M
74VHC86SJ
74VHC86MTC
74VHC86MTCX_NL
(Note 1)
74VHC86N
Package
Number
M14A
M14D
MTC14
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STS-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Truth Table
Pin Descriptions
Pin Names
A
0
鈥揂
3
B
0
鈥揃
3
O
0
鈥揙
3
Description
Inputs
Inputs
Outputs
DS011517
A
L
L
H
H
B
L
H
L
H
O
L
H
H
L
www.fairchildsemi.com
漏 2005 Fairchild Semiconductor Corporation
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