80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor
Data Sheet
Advance Information
Product Features
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32-Bit Parallel Architecture
鈥擫oad/Store Architecture
鈥擲ixteen 32-Bit Global Registers
鈥擲ixteen 32-Bit Local Registers
鈥?.28 Gbyte Internal Bandwidth
(80 MHz)
鈥擮n-Chip Register Cache
Processor Core Clock
鈥?0960HA is 1x Bus Clock
鈥?0960HD is 2x Bus Clock
鈥?0960HT is 3x Bus Clock
Binary Compatible with Other 80960
Processors
Issue Up To 150 Million Instructions per
Second
High-Performance On-Chip Storage
鈥?6 Kbyte Four-Way Set-Associative
Instruction Cache
鈥? Kbyte Four-Way Set-Associative Data
Cache
鈥? Kbyte General Purpose RAM
鈥擲eparate 128-Bit Internal Paths For
Instructions/Data
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3.3 V Supply Voltage
鈥? V Tolerant Inputs
鈥擳TL Compatible Outputs
Guarded Memory Unit
鈥擯rovides Memory Protection
鈥擴ser/Supervisor Read/Write/Execute
32-Bit Demultiplexed Burst Bus
鈥擯er-Byte Parity Generation/Checking
鈥擜ddress Pipelining Option
鈥擣ully Programmable Wait State
Generator
鈥擲upports 8-, 16- or 32-Bit Bus Widths
鈥?60 Mbyte/s External Bandwidth
(40 MHz)
High-Speed Interrupt Controller
鈥擴p to 240 External Interrupts
鈥?1 Fully Programmable Priorities
鈥擲eparate, Non-maskable Interrupt Pin
Dual On-Chip 32-Bit Timers
鈥擜uto Reload Capability and One-Shot
鈥擟LKIN Prescaling, 梅1, 2, 4 or 8
鈥擩TAG Support - IEEE 1149.1 Compliant
Notice:
This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 272495-007
July, 1998