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83025022A Datasheet

  • 83025022A

  • SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-...

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  • 20页

  • TI

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SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A 鈥?APRIL 1982 鈥?REVISED JANUARY 1995
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
3-State Q Outputs Drive Bus Lines Directly
Counter Operation Independent of 3-State
Output
Fully Synchronous Clear, Count, and Load
Asynchronous Clear Is Also Provided
Fully Cascadable
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
SN54ALS569A . . . J PACKAGE
SN74ALS568A, SN74ALS569A . . . DW OR N PACKAGE
(TOP VIEW)
description
The SN74ALS568A decade counter and
鈥睞LS569A
binary counters are programmable,
count up or down, and offer both synchronous and
asynchronous clearing. All synchronous functions
are executed on the positive-going edge of the
clock (CLK) input.
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR) or
synchronous clear (SCLR). Asynchronous (direct)
clearing overrides all other functions of the device,
while synchronous clearing overrides only the
other synchronous functions. Data is loaded from
the A, B, C, and D inputs by holding load (LOAD)
low during a positive-going clock transition. The
counting function is enabled only when enable P
(ENP) and enable T (ENT) are low and ACLR,
SCLR, and LOAD are high. The up/down (U/D)
input controls the direction of the count. These
counters count up when U/D is high and count
down when U/D is low.
U/D
CLK
A
B
C
D
ENP
ACLR
SCLR
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
RCO
CCO
OE
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
SN54ALS569A . . . FK PACKAGE
(TOP VIEW)
A
CLK
B
C
D
ENP
ACLR
3
4
5
6
7
8
2 1 20 19
18
17
16
15
U/D
V
CC
RCO
CCO
OE
Q
A
Q
B
Q
C
14
9 10 11 12 13
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output
(RCO) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum
(9 or 15) when counting up. The clocked carry output (CCO) produces a low-level pulse for a duration equal to
that of the low level of the clock when RCO is low and the counter is enabled (both ENP and ENT are low);
otherwise, CCO is high. CCO does not have the glitches commonly associated with a ripple-carry output.
Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter.
However, for very high-speed counting, RCO should be used for cascading since CCO does not become active
until the clock returns to the low level.
The SN54ALS569A is characterized for operation over the full military temperature range of 鈥?55掳C to 125掳C.
The SN74ALS568A and SN74ALS569A are characterized for operation from 0掳C to 70掳C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
SCLR
GND
LOAD
ENT
Q
D
1

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