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ADC10065CIMT Datasheet

  • ADC10065CIMT

  • ADC10065 10-Bit 65 MSPS 3V A/D Converter

  • 942.17KB

  • 19页

  • NSC

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ADC10065 10-Bit 65 MSPS 3V A/D Converter
May 2005
ADC10065
10-Bit 65 MSPS 3V A/D Converter
General Description
The ADC10065 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 10-bit
digital words at 65 Megasamples per second (MSPS). This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
provide a complete conversion solution, and to minimize
power consumption, while providing excellent dynamic per-
formance. A unique sample-and-hold stage yields a full-
power bandwidth of 400 MHz. Operating on a single 3.0V
power supply, this device consumes just 68.4 mW at
65 MSPS, including the reference current. The Standby
feature reduces power consumption to just 14 .1 mW.
The differential inputs provide a full scale selectable input
swing of 2.0 V
P-P
, 1.5 V
P-P
, 1.0 V
P-P
, with the possibility of a
single-ended input. Full use of the differential input is recom-
mended for optimum performance. An internal +1.2V preci-
sion bandgap reference is used to set the ADC full-scale
range, and also allows the user to supply a buffered refer-
enced voltage for those applications requiring increased ac-
curacy. The output data format is 10-bit offset binary, or two鈥檚
complement.
This device is available in the 28-lead TSSOP package and
will operate over the industrial temperature range of 鈭?0藲C to
+85藲C.
Features
n
Single +3.0V operation
n
Selectable 2.0 V
P-P
, 1.5 V
P-P
, or 1.0 V
P-P
full-scale input
swing
n
400 MHz 鈭? dB input bandwidth
n
Low power consumption
n
Standby mode
n
On-chip reference and sample-and-hold amplifier
n
Offset binary or two鈥檚 complement data format
n
Separate adjustable output driver supply to
accommodate 2.5V and 3.3V logic families
n
28-pin TSSOP package
Key Specifications
n
n
n
n
n
n
n
n
n
Resolution
Conversion Rate
Full Power Bandwidth
DNL
SNR (f
IN
= 11 MHz)
SFDR (f
IN
= 11 MHz)
Data Latency
Supply Voltage
Power Consumption, 65 MHz
10 Bits
65 MSPS
400 MHz
卤
0.3 LSB (typ)
59.6 dB (typ)
鈭?0 dB (typ)
6 Clock Cycles
+3.0V
68.4 mW
Applications
n
n
n
n
n
n
n
n
Ultrasound and Imaging
Instrumentation
Cellular Based Stations/Communications Receivers
Sonar/Radar
xDSL
Wireless Local Loops
Data Acquisition Systems
DSP Front Ends
Connection Diagram
20077901
漏 2005 National Semiconductor Corporation
DS200779
www.national.com

ADC10065CIMT 产品属性

  • National Semiconductor (TI)

  • 1

  • 1

  • Pipelined

  • 65000 KSPs

  • 10 bit

  • Voltage

  • Parallel

  • 59.6 dB

  • Internal, External

  • 3.6 V

  • 2.7 V

  • 68.4 mW

  • + 85 C

  • SMD/SMT

  • TSSOP-28

  • Tube

  • - 40 C

  • 3 V

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