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ADSP-2184N Datasheet

  • ADSP-2184N

  • Analog Devices [DSP Microcomputer]

  • 1458.04KB

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a
PERFORMANCE FEATURES
12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 200 CLKIN Cycle Recovery
from Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION FEATURES
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
Up to 256K Bytes of On-Chip RAM, Configured as
Up to 48K Words Program Memory RAM
Up to 56K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
DSP Microcomputer
ADSP-218xN Series
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
SYSTEM INTERFACE FEATURES
Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to On-
Chip Memory (Mode Selectable)
4M-Byte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program and
Data Memory Transfers (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits 鈥淕lueless鈥?System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or through
Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT
Reconfiguration
ICE-Port鈩?Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
FULL MEMORY MODE
MEMORY
DATA ADDRESS
GENERATORS
DAG1
DAG2
PROGRAM
SEQUENCER
PROGRAM
MEMORY
UP TO
48K 24-BIT
DATA
MEMORY
UP TO
56K 16-BIT
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
TIMER
INTERNAL
DMA
PORT
HOST MODE
hip
tc
er
Ins
ck
blo
PROGRAM MEMORY ADDRESS
ram
iag
d
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
.
ere
h
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT0
SPORT1
ADSP-2100 BASE
ARCHITECTURE
ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reli-
able. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
http://www.analog.com
Fax:781/326-8703
漏 Analog Devices, Inc., 2001

ADSP-2184N PDF文件相关型号

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