Plerow APL4500
PLL Module
Features
路
-4 dBm Output Level at 4500 MHz
路
Channel Step Size : 1000 kHz
路
2
nd
Description
The plerow PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB鈥檚 PLL provides
exceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are
available in a surface-mount type package.
TM
Harmonic : < 0 dBc
< 10 ms
路
Spurious Level : < -70 dBc
路
Lock Time :
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25 mA Current Consumption
Specifications
Parameter
Frequency Range
Output Power
Supply Voltage
Current Consumption
Channel Step Size
2
nd
Harmonics
Spurious Level
Lock Time
Reference Frequency
Reference Input Level
Phase Noise (C / N)
@ 10 kHz
@ 100 kHz
Output Impedance
Operating Temp. Range
Package Type & Size
dBc/Hz
dBc/Hz
鈩?/div>
掳C
Mm
-40
-96
-123
-93
-120
50
25
SMT, 19.0W脳19.0L脳5.8H
85
-90
-117
Unit
MHz
dBm
V
mA
kHz
dBc
dBc
ms
MHz
dBm
-5
-5
4.7
Min.
Typical
4500
-4
5.0
25
1000
-4
-78
3
10
0
5
0
-70
10
-3
5.3
35
Max.
More Information
Website: www.asb.co.kr
E-mail: sales@asb.co.kr
Tel: (82) 42-528-7220
Fax: (82) 42-528-7222
ASB, Inc., 4
th
Fl. Venture Town
Bldg, KT HRDC, 367-17
Goijeong-Dong, Seo-Gu,
Daejeon, 302-716, Korea
1) Measurement conditions are as follows: T = 25掳C, V
CC
= 5 V, Freq. = 4500 MHz, 50 ohm system.
Outline Drawing
Top View
Bottom View
Pin Configuration
Dimension (mm)
A
B
C
D
E
F
G
19.0
19.0
5.8
1.5
0.5
1.75
1.35
D
A
E
F
I
C
B
Side View
1/1
www.asb.co.kr
H
G
1
2
3
4
9
13
15
16
Others
CLOCK
DATA
ENABLE
OSC IN
VCC (VCO)
RF OUT
VCP (PLL)
LOCK DETECT
Ground
H
15.0
I
0.9
Tolerance:
卤
0.2
March 2004
1
