High Performance
32K
脳
8
CMOS SRAM
32K
脳
8 CMOS SRAM (Common I/O)
FEATURES
鈥?Organization: 32,768 words
脳
8 bits
鈥?High speed
鈥?10/12/15/20/25/35 ns address access time
鈥?3/3/4/5/6/8 ns output enable access time
鈥?Low power consumption
鈥?Active:
鈥?Standby:
660 mW max (10 ns cycle)
11 mW max, CMOS I/O
2.75 mW max, CMOS I/O, L version
鈥?Equal access and cycle times
AS7C256
AS7C256L
鈥?Easy memory expansion with CE and OE inputs
鈥?TTL-compatible, three-state I/O
鈥?28-pin JEDEC standard packages
鈥?300 mil PDIP and SOJ
Socket compatible with 7C512 and 7C1024
鈥?330 mil SOIC
鈥?8脳13.4 TSOP
鈥?ESD protection > 2000 volts
鈥?Latch-up current > 200 mA
鈥?Very low DC component in active power
鈥?2.0V data retention (L version)
LOGIC BLOCK DIAGRAM
PIN ARRANGEMENT
DIP, SOJ, SOIC
Vcc
GND
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A14
ROW DECODER
I/O7
256脳128脳8
ARRAY
(262,144)
SENSE AMP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
COLUMN DECODER
WE
CONTROL
CIRCUIT
OE
CE
TSOP 8
脳
13.4
A A A A A A A
7 8 9 10 11 12 13
AS7C256-01
SELECTION GUIDE
7C256-10
Maximum Address Access Time
Maximum Output Enable Access Time
Maximum Operating Current
Maximum CMOS Standby Current
10
3
120
2.0
L
0.5
7C256-12
12
3
115
2.0
0.5
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
AS7C256
AS7C256
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
AS7C256-02
A1
A2
7C256-15
15
4
110
2.0
0.5
7C256-20
20
5
100
2.0
0.5
7C256-25
25
6
90
2.0
0.5
7C256-35
35
8
80
2.0
0.5
Unit
ns
ns
mA
mA
mA
ALLIANCE SEMICONDUCTOR
1
2
3
4
5
6
7
8
