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ATV5000数据手册封面

ATV5000 Datasheet

  • ATV5000

  • IC,COMPLEX-EPLD,76-CELL,25NS PROP DELAY,LDCC,68PIN,PLASTIC

  • 742.88KB

  • Atmel   Atmel

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ATV5000/L
Features
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Advanced Programmable Logic Device - High Gate Utilization
Flexible Interconnect Architecture - Universal Routing
Flexible Logic Cells - 128 Flip-Flops and 52 Latches
Multiple Flip-Flop Types - Synchronous or Asynchronous Registers
High Speed - 50 MHz Operation
Complete Third Party Software Support
No Placement, Routing or Layout Software Required
Proven and Reliable High Speed CMOS EPROM Process
2000 V ESD Protection
200 mA Latchup Immunity
Reprogrammable - Tested 100% for Programmability
Commercial, Industrial and Military Temperature Grades
Block Diagram
52 INPUT
LATCHES
High Density
UV Erasable
Programmable
Logic Device
8
INPUT
PINS
UNIVERSAL
AND
REGIONAL
INTERCONNECT
52 LOGIC CELLS
(104 FLIP-FLOPS)
52
I/O
PINS
24 BURIED CELLS
(24 FLIP-FLOPS)
Description
The Atmel V5000 is an easy to use, high density programmable logic device. Its simple, regu-
lar architecture translates into increased utilization and high performance.
The ATV5000 has one programmable combinatorial logic array. This guarantees easy inter-
connection of and uniform performance from all nodes. "Sum terms", which are easy to use
groupings of AND-OR gates, provide combinatorial logic blocks. Sum terms can be wire-
OR鈥檇 together to integrate larger logic blocks. To expand the levels of logic, buried sum terms
feed back into the logic array. The 52 I/O pins can each be driven by a register or a sum term.
Each I/O pin has an individually enabled input latch.
All 128 registers are configurable as D- or T-types without using extra logic gates. Individual
sum terms, asynchronous presets, resets and clocks give each flip-flop added flexibility. A
direct "clock from pin" option guarantees synchronization and fast clock to output perform-
ance.
Standard, off-the-shelf third-party software tools and programmers support the ATV5000.
This minimizes start-up investment and improves product support.
JLCC
Chip Carrier
Pin Configuration
Pin Name
IN
Pins 2,32,36,66
Pins 1,34,35,68
I/O
VCC
Function
Logic and Clock Inputs
Input/Register Clocks 1-4
Input/Latch Clocks 1-4
Bidirectional Buffers
+5 V Supply
I/Os
GND
I/Os
VCC
18
I/Os
VCC
I/Os
IN
1
GND
IN
I/Os
I/Os
VCC
52
I/Os
GND
I/Os
35
I/Os
IN
GND
IN
VCC
I/Os
0065B
1-193

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