CD4020BMS, CD4024BMS,
CD4040BMS
October 1996
CMOS Ripple-Carry Binary
Counter/Dividers
Pinouts
CD4020BMS
TOP VIEW
Features
鈥?High Voltage Types (20V Rating)
鈥?Medium Speed Operation
鈥?Fully Static Operation
鈥?Buffered Inputs and Outputs
鈥?100% Tested for Quiescent Current at 20V
鈥?Standardized Symmetrical Output Characteristics
鈥?Common Reset
鈥?5V, 10V and 15V Parametric Ratings
鈥?Maximum Input Current of 1碌a at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25
o
C
鈥?Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
鈥?Meets All Requirements of JEDEC Tentative Standard
No. 13B, 鈥淪tandard Speci铿乧ations For Description Of
鈥楤鈥?Series CMOS Devices鈥?/div>
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
VSS 8
16 VDD
15 Q11
14 Q10
13 Q8
12 Q9
11 RESET
10
胃
9 Q1
CD4024BMS
TOP VIEW
胃
1
RESET 2
Q7 3
Q6 4
Q5 5
Q4 6
VSS 7
14 VDD
13 NC
12 Q1
11 Q2
10 NC
9 Q3
8 NC
Applications
鈥?Control Counters
鈥?Timers
鈥?Frequency Dividers
鈥?Time-Delay Circuits
Description
NC = NO CONNECTION
CD4020BMS - 14 Stage
CD4024BMS - 7 Stage
CD4040BMS - 12 Stage
CD4020BMS, CD4024BMS, and CD4040BMS are ripple-
carry binary counters. All counter stages are master-slave
铿俰p-铿俹ps. The state of a counter advances one count on the
negative transition of each input pulse; a high level on the
RESET line resets the counter to its all zeros state. Schmitt
trigger action on the input-pulse line permits unlimited rise
and fall times. All inputs and outputs are buffered.
The CD4020BMS, CD4024BMS and the CD4040BMS is
supplied in these 14 lead outline packages:
CD4020B
CD4024B
H4Q
H1B
H3W
CD4040B
H4X
H1F
H6W
Q12 1
Q6 2
Q5 3
Q7 4
Q4 5
Q3 6
Q2 7
VSS 8
CD4040BMS
TOP VIEW
16 VDD
15 Q11
14 Q10
13 Q8
12 Q9
11 R
10
胃
9 Q1
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H1F
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
File Number
3300.1
7-359
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