CD4060BMS
December 1992
CMOS 14 Stage Ripple-Carry
Binary Counter/Divider and Oscillator
Pinout
Q12 1
Q13 2
16 VDD
15 Q10
14 Q8
13 Q9
12 RESET
11 酶I
10 酶
0
9 酶
0
Features
鈥?High Voltage Type (20V Rating)
鈥?Common Reset
鈥?12MHz Clock Rate at 15V
鈥?Fully Static Operation
鈥?Buffered Inputs and Outputs
鈥?Schmitt Trigger Input Pulse Line
鈥?Standardized, Symmetrical Output Characteristics
鈥?100% Tested for Quiescent Current at 20V
鈥?5V, 10V and 15V Parametric Ratings
鈥?Meets All Requirements of JEDEC Tentative Standard
No. 13B, 鈥淪tandard Speci铿乧ations for Description of
鈥楤鈥?Series CMOS Devices鈥?/div>
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
VSS 8
Functional Diagram
Q4
Q5
Q6
R 12
14 STAGE
RIPPLE
COUNTER
AND
OSCILLATOR
酶I 11
Q7
Q8
Q9
Q10
Q12
Oscillator Features
鈥?All Active Components on Chip
鈥?RC or Crystal Oscillator Con铿乬uration
鈥?RC Oscillator Frequency of 690kHz Min. at 15V
7
5
4
6
14
13
15
1
2
3
Applications
鈥?Control counters
鈥?Timers
鈥?Frequency Dividers
鈥?Time Delay Circuits
VSS = 8
VDD = 16
Q13
Q14
Description
CD4060BMS consists of an oscillator section and 14 ripple
carry binary counter stages. The oscillator con铿乬uration allows
design of either RC or crystal oscillator circuits. A RESET input
is provided which resets the counter to the all O鈥檚 state and dis-
ables the oscillator. A high level on the RESET line accom-
plishes the reset function. All counter stages are master slave
铿俰p-铿俹ps. The state of the counter is advanced one step in
binary order on the negative transition of 酶I (and 酶
0
). All inputs
and outputs are fully buffered. Schmitt trigger action on the
input pulse line permits unlimited input pulse rise and fall times.
The CD4060BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H1F
H6W
酶
0
9
酶
0
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
File Number
3317
7-949
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