CD54HC4059, CD74HC4059
Data sheet acquired from Harris Semiconductor
SCHS206B
February 1998 - Revised May 2003
High-Speed CMOS Logic
CMOS Programmable Divide-by-N Counter
Description
The 鈥橦C4059 are high-speed silicon-gate devices that are
pin-compatible with the CD4059A devices of the CD4000B
series. These devices are divide-by-N down-counters that
can be programmed to divide an input frequency by any
number 鈥淣鈥?from 3 to 15,999. The output signal is a pulse
one clock cycle wide occurring at a rate equal to the input
frequency divide by N. The down-counter is preset by means
of 16 jam inputs.
The three Mode-Select Inputs K
a
, K
b
and K
c
determine the
modulus (鈥渄ivide-by鈥?number) of the first and last counting
sections in accordance with the truth table. Every time the first
(fastest) counting section goes through one cycle, it reduces by
1 the number that has been preset (jammed) into the three
decades of the intermediate counting section an the last
counting section, which consists of flip-flops that are not
needed for opening the first counting section. For example, in
the
梅2
mode, only one flip-flop is needed in the first counting
section. Therefore the last counting section has three flip-flops
that can be preset to a maximum count of seven with a place
value of thousands. If
梅10
is desired for the first section, K
a
is
set 鈥渉igh鈥? K
b
鈥渉igh鈥?and K
c
鈥渓ow鈥? Jam inputs J1, J2, J3, and J4
are used to preset the first counting section and there is no last
counting section. The intermediate counting section consists of
three cascaded BCD decade (梅10) counters presettable by
means of Jam Inputs J5 through J16.
The Mode-Select Inputs permit frequency-synthesizer
channel separations of 10, 12.5, 20, 25 or 50 parts. These
inputs set the maximum value of N at 9999 (when the 铿乺st
counting section divides by 5 or 10) or 15,999 (when the 铿乺st
counting section divides by 8, 4, or 2).
The three decades of the intermediate counter can be preset
to a binary 15 instead of a binary 9, while their place values
are still 1, 10, and 100, multiplied by the number of the
梅N
mode. For example, in the
梅8
mode, the number from which
counting down begins can be preset to:
3rd Decade
1500
2nd Decade
150
1st Decade
15
Last Counting Section
1000
The total of these numbers (2665) times 8 equals 12,320.
The 铿乺st counting section can be preset to 7. Therefore,
21,327 is the maximum possible count in the
梅8
mode.
The highest count of the various modes is shown in the
Extended Counter Range column. Control inputs K
b
and K
c
can be used to initiate and lock the counter in the 鈥渕aster
preset鈥?state. In this condition the flip-flops in the counter are
preset in accordance with the jam inputs and the counter
remains in that state as long as K
b
and K
c
both remain low. The
counter begins to count down from the preset state when a
counting mode other than the master preset mode is selected.
Features
[ /Title
(CD74
HC4059
)
/Sub-
ject
(High-
Speed
CMOS
Logic
CMOS
Pro-
鈥?Synchronous Programmable
梅N
Counter N = 3 to 9999
or 15999
鈥?Presettable Down-Counter
鈥?Fully Static Operation
鈥?Mode-Select Control of Initial Decade Counting
Function (梅10, 8, 5, 4, 2)
鈥?Master Preset Initialization
鈥?Latchable
梅N
Output
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi铿乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
Applications
鈥?Communications Digital Frequency Synthesizers;
VHF, UHF, FM, AM, etc.
鈥?Fixed or Programmable Frequency Division
鈥?鈥淭ime Out鈥?Timer for Consumer-Application Industrial
Controls
Ordering Information
PART NUMBER
CD54HC4059F3A
CD74HC4059E
CD74HC4059M96
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
PACKAGE
24 Ld CERDIP
24 Ld PDIP
24 Ld SOIC
NOTE: When ordering, use the entire part number. The suf铿亁 96
denotes tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
1
1
2
3
4
5
6
7
8
9
10
11
12
