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CD74HC109 Datasheet

  • CD74HC109

  • High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-...

  • 288.00KB

  • 13页

  • TI

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Data sheet acquired from Harris Semiconductor
SCHS140
CD74HC109,
CD74HCT109
Dual J-K Flip-Flop with Set and Reset
Positive-Edge Trigger
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A at V
OL
, V
OH
March 1998
Features
鈥?Asynchronous Set and Reset
鈥?Schmitt Trigger Clock Inputs
鈥?Typical Propagation Delay = 18ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
鈥?Typical f
MAX
= 60MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi铿乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
[ /Title
(CD74H
C109,
CD74H
CT109)
/Subject
(Dual J-
K Flip-
Flop
with Set
and
Reset
Description
The Harris CD74HC109 and CD74HCT109 are dual J-K 铿俰p-
铿俹ps with set and reset. The 铿俰p-铿俹p changes state with the
positive transition of Clock (1CP and 2CP).
The 铿俰p-铿俹p is set and reset by active-low S and R,
respectively. A low on both the set and reset inputs
simultaneously will force both Q and Q outputs high.
However, both set and reset going high simultaneously
results in an unpredictable output condition.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG.
NO.
Pinout
CD74HC109, CD74HCT109
(PDIP, SOIC)
TOP VIEW
1R 1
1J 2
1K 3
1CP 4
1S 5
1Q 6
1Q 7
GND 8
16 V
CC
15 2R
14 2J
13 2K
12 2CP
11 2S
10 2Q
9 2Q
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1998
File Number
1667.1
1

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