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CD74HC147ME4 Datasheet

  • CD74HC147ME4

  • High-Speed CMOS Logic 10- to 4-Line Priority Encoder

  • 347.10KB

  • 13页

  • TI

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CD54HC147, CD74HC147,
CD74HCT147
Data sheet acquired from Harris Semiconductor
SCHS149F
September 1997 - Revised November 2003
High-Speed CMOS Logic
10- to 4-Line Priority Encoder
provide binary representation on the four active LOW inputs
(Y0 to Y3). A priority is assigned to each input so that when
two or more inputs are simultaneously active, the input with
the highest priority is represented on the output, with input
line l
9
having the highest priority.
These devices provide the 10-line to 4-line priority encoding
function by use of the implied decimal 鈥渮ero鈥? The 鈥渮ero鈥?is
encoded when all nine data inputs are HIGH, forcing all four
outputs HIGH.
[ /Title
(CD74
HC147
,
CD74
HCT14
7)
/Sub-
ject
(High
Speed
CMOS
Logic
10-to-4
Line
Prior-
ity
Encode
r)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
10-to-4
Line
Prior-
ity
Encode
r, High
Speed
CMOS
Logic
10-to-4
Line
Prior-
ity
Features
鈥?Buffered Inputs and Outputs
鈥?Typical Propagation Delay: 13ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi铿乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC147F3A
CD74HC147E
CD74HC147M
CD74HC147MT
CD74HC147M96
CD74HC147NSR
CD74HC147PW
CD74HC147PWR
CD74HC147PWT
CD74HCT147E
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
Description
The 鈥橦C147 and CD74HCT147 are high speed silicon-gate
CMOS devices and are pin-compatible with low power
Schottky TTL (LSTTL).
The 鈥橦C147 and CD74HCT147 9-input priority encoders
accept data from nine active LOW inputs (l
1
to l
9
) and
NOTE: When ordering, use the entire part number. The suf铿亁es
96 and R denote tape and reel. The suf铿亁 T denotes a
small-quantity reel of 250.
Pinout
CD54HC147 (CERDIP)
CD74HC147 (PDIP, SOIC, SOP, TSSOP)
CD74HCT147 (PDIP, TSSOP)
TOP VIEW
I4 1
I5 2
I6 3
I7 4
I8 5
Y2 6
Y1 7
GND 8
16 V
CC
15 NC
14 Y3
13 I3
12 I2
11 I1
10 I9
9 Y0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
1

CD74HC147ME4 产品属性

  • 40

  • 集成电路 (IC)

  • 逻辑 - 信号开关，多路复用器，解码器

  • 74HC

  • 优先顺序编码器

  • 1 x 10:4

  • 1

  • 5.2mA，5.2mA

  • 单电源

  • 2 V ~ 6 V

  • -55°C ~ 125°C

  • 表面贴装

  • 16-SOIC（0.154"，3.90mm 宽）

  • 16-SOIC N

  • 管件

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