Data sheet acquired from Harris Semiconductor
SCHS192
CD74HC640,
CD74HCT640
High Speed CMOS Logic
Octal Three-State Bus Transceiver, Inverting
(PDIP, SOIC)
TOP VIEW
January 1998
Features
鈥?Buffered Inputs
鈥?Three-State Outputs
鈥?Applications in Multiple-Data-Bus Architecture
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi铿乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A at V
OL
, V
OH
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
[ /Title
(CD74
HC640
,
CD74
HCT64
0)
/Sub-
ject
(High
Speed
CMOS
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
GND 10
Description
The Harris CD74HC640 and CD74HCT640 silicon-gate
CMOS three-state bidirectional inverting and non-inverting
buffers are intended for two-way asynchronous
communication between data buses. They have high drive
current outputs which enable high-speed operation when
driving large bus capacitances. These circuits possess the
low power dissipation of CMOS circuits, and have speeds
comparable to low power Sckottky TTL circuits. They can
drive 15 LSTTL loads. The CD74HC640 and CD74HCT640
are inverting buffers.
Pinout
CD74HC640, CD74HCT640
Functional Diagram
A0
B0
A1
THRU
A6
B1
THRU
B6
A7
B7
OE
DIR
OUTPUT ENABLE AND
DIRECTION-SELECT LOGIC
V
CC
= 20
GND = 10
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1998
File Number
1677.1
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