Data sheet acquired from Harris Semiconductor
SCHS134
CD74HC73,
CD74HCT73
Dual J-K Flip-Flop with Reset
Negative-Edge Trigger
Description
The Harris CD74HC73 and CD74HCT73 utilize silicon gate
CMOS technology to achieve operating speeds equivalent to
LSTTL parts. They exhibit the low power consumption of
standard CMOS integrated circuits, together with the ability
to drive 10 LSTTL loads.
These 铿俰p-铿俹ps have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input. This
device is functionally identical to the HC/HCT107 but differs
in terminal assignment and in some parametric limits.
The 74HCT logic family is functionally as well as pin
compatible with the standard 74LS logic family.
February 1998
Features
鈥?Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
鈥?Asynchronous Reset
鈥?Complementary Outputs
鈥?Buffered Inputs
鈥?Typical f
MAX
= 60MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi铿乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A at V
OL
, V
OH
[ /Title
(CD74
HC73,
CD74
HCT73
)
/Sub-
ject
(Dual
J-K
Flip-
Flop
Ordering Information
PART NUMBER
CD74HC73E
CD74HCT73E
CD74HC73M
NOTES:
6. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
7. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld PDIP
14 Ld PDIP
14 Ld SOIC
PKG.
NO.
E14.3
E14.3
M14.15
Pinout
CD74HC73, CD74HCT73
(PDIP, SOIC)
TOP VIEW
1CP 1
1R 2
1K 3
V
CC
4
2CP 5
2R 6
2J 7
14 1J
13 1Q
12 1Q
11 GND
10 2K
9 2Q
8 2Q
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1998
File Number
1721.1
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