鈮?/div>
1碌A at V
OL
, V
OH
鈥?Related Literature
- CD54HC10F3A and CD54HCT10F3A Military
Data Sheet, Document Number 3758
August 1997
[ /Title
(CD74
HC10,
CD74
HCT10
)
/Sub-
ject
(High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate,
High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate,
Harris
Semi-
Features
鈥?Buffered Inputs
鈥?Typical Propagation Delay: 8ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi铿乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
Description
The Harris CD74HC10, CD74HCT10, logic gates utilize
silicon gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The 74HCT logic family is
Pinout
CD74HC10, CD74HCT10
(PDIP, SOIC)
TOP VIEW
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
14 V
CC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1997
File Number
1551.1
1
1
2
3
4
5
6
