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CD74HCT40105M96E4 Datasheet

  • CD74HCT40105M96E4

  • High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register

  • 317.75KB

  • 19页

  • TI

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CD54HC40105, CD74HC40105,
CD54HCT40105, CD74HCT40105
Data sheet acquired from Harris Semiconductor
SCHS222C
February 1998 - Revised October 2003
High-Speed CMOS Logic
4-Bit x 16-Word FIFO Register
Description
The 鈥橦C40105 and 鈥橦CT40105 are high-speed silicon-gate
CMOS devices that are compatible, except for 鈥渟hift-out鈥?/div>
circuitry, with the CD40105B. They are low-power 铿乺st-in-out
(FIFO) 鈥渆lastic鈥?storage registers that can store 16 four-bit
words. The 40105 is capable of handling input and output
data at different shifting rates. This feature makes it
particularly useful as a buffer between asynchronous
systems.
Each work position in the register is clocked by a control 铿俰p-
铿俹p, which stores a marker bit. A 鈥?鈥?signi铿乪s that the posi-
tion鈥檚 data is 铿乴led and a 鈥?鈥?denotes a vacancy in that posi-
tion. The control 铿俰p-铿俹p detects the state of the preceding
铿俰p-铿俹p and communicates its own status to the succeeding
铿俰p-铿俹p. When a control 铿俰p-铿俹p is in the 鈥?鈥?state and sees a
鈥?鈥?in the preceeding 铿俰p-铿俹p, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding 铿俰p-铿俹p to
鈥?鈥? The 铿乺st and last control 铿俰p-铿俹ps have buffered outputs.
Since all empty locations 鈥渂ubble鈥?automatically to the input
end, and all valid data ripple through to the output end, the
status of the 铿乺st control 铿俰p-铿俹p (DATA-IN READY) indicates
if the FIFO is full, and the status of the last 铿俰p-铿俹p (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
Features
鈥?Independent Asynchronous Inputs and Outputs
[ /Title
(CD74
HC401
05,
CD74
HCT40
105)
/Sub-
ject
(High
Speed
CMOS
鈥?Expandable in Either Direction
鈥?Reset Capability
鈥?Status Indicators on Inputs and Outputs
鈥?Three-State Outputs
鈥?Shift-Out Independent of Three-State Control
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi铿乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC40105F3A
CD54HCT40105F3A
CD74HC40105E
CD74HC40105M
CD74HC40105MT
CD74HC40105M96
CD74HCT40105E
CD74HCT40105M
CD74HCT40105MT
CD74HCT40105M96
TEMP. RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
Applications
鈥?Bit-Rate Smoothing
鈥?CPU/Terminal Buffering
鈥?Data Communications
鈥?Peripheral Buffering
鈥?Line Printer Input Buffers
鈥?Auto-Dialers
鈥?CRT Buffer Memories
鈥?Radar Data Acquisition
NOTE: When ordering, use the entire part number. The suf铿亁 96
denotes tape and reel. The suf铿亁 T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
1

CD74HCT40105M96E4 产品属性

  • 2,500

  • 集成电路 (IC)

  • 逻辑 - FIFO

  • 74HCT

  • 异步

  • 64 (16 x 4)

  • -

  • -

  • 4.5 V ~ 5.5 V

  • -55°C ~ 125°C

  • 表面贴装

  • 16-SOIC（0.154"，3.90mm 宽）

  • 16-SOIC N

  • 带卷 (TR)

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