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CY7C68013A Datasheet

  • CY7C68013A

  • EZ-USB FX2LP? USB Microcontroller

  • 68.00KB

  • 0页

  • CYPRESS

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CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
EZ-USB FX2LP鈩?USB Microcontroller
1.0
Features (CY7C68013A/14A/15A/16A)
鈥?USB 2.0鈥揢SB-IF high speed certified (TID # 40440111)
鈥?Single-chip integrated USB 2.0 transceiver, smart SIE,
and enhanced 8051 microprocessor
鈥?Fit, form and function compatible with the FX2
鈥?Pin-compatible
鈥?Object-code-compatible
鈥?Functionally-compatible (FX2LP is a superset)
鈥?Ultra Low power: I
CC
no more than 85 mA in any mode
鈥?Ideal for bus and battery powered applications
鈥?Software: 8051 code runs from:
鈥?Internal RAM, which is downloaded via USB
鈥?Internal RAM, which is loaded from EEPROM
鈥?External memory device (128 pin package)
鈥?16 KBytes of on-chip Code/Data RAM
鈥?Four programmable BULK/INTERRUPT/ISOCHRO-
NOUS endpoints
鈥?Buffering options: double, triple, and quad
鈥?Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
鈥?8- or 16-bit external data interface
鈥?Smart Media Standard ECC generation
鈥?GPIF (General Programmable Interface)
鈥?Allows direct connection to most parallel interface
鈥?Programmable waveform descriptors and configu-
ration registers to define waveforms
鈥?Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
24 MHz
Ext. XTAL
High-performance micro
using standard tools
with lower-power options
Address (16)
鈥?/div>
Integrated, industry-standard enhanced 8051
鈥?48-MHz, 24-MHz, or 12-MHz CPU operation
鈥?Four clocks per instruction cycle
鈥?Two USARTS
鈥?Three counter/timers
鈥?Expanded interrupt system
鈥?Two data pointers
鈥?/div>
3.3V operation with 5V tolerant inputs
鈥?/div>
Vectored USB interrupts and GPIF/FIFO interrupts
鈥?/div>
Separate data buffers for the Set-up and Data portions
of a CONTROL transfer
鈥?/div>
Integrated I
2
C controller, runs at 100 or 400 kHz
鈥?/div>
Four integrated FIFOs
鈥?Integrated glue logic and FIFOs lower system cost
鈥?Automatic conversion to and from 16-bit buses
鈥?Master or slave operation
鈥?Uses external clock or asynchronous strobes
鈥?Easy interface to ASIC and DSP ICs
1.1
Features (CY7C68013A/14A only)
鈥?CY7C68014A: Ideal for battery powered applications
鈥?Suspend current: 100
碌A
(typ)
鈥?CY7C68013A: Ideal for non-battery powered applica-
tions
鈥?Suspend current: 300
碌A
(typ)
鈥?Available in four lead-free packages with up to 40 GPIOs
鈥?128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs),
56-pin QFN (24 GPIOs) and 56-pin SSOP (24 GPIOs)
Data (8)
FX2LP
Address (16) / Data Bus (8)
VCC
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
Master
Additional I/Os (24)
1.5k
connected for
full speed
D+
D鈥?/div>
Integrated
full- and high-speed
XCVR
USB
2.0
XCVR
CY
Smart
USB
1.1/2.0
Engine
16 KB
RAM
Abundant I/O
including two USARTS
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
ADDR (9)
GPIF
ECC
RDY (6)
CTL (6)
4 kB
FIFO
8/16
Up to 96 MBytes/s
burst rate
Enhanced USB core
Simplifies 8051 code
鈥淪oft Configuration鈥?/div>
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08032 Rev. *G
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 1, 2005

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