DM74AS244 Datasheet

  • DM74AS244

  • 3-STATE Bus Driver/Receiver

  • 53.71KB

  • fairchild

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DM74AS240 鈥?DM74AS244 3-STATE Bus Driver/Receiver
October 1986
Revised March 2000
DM74AS240 鈥?DM74AS244
3-STATE Bus Driver/Receiver
General Description
This family of Advance Schottky 3-STATE Bus circuits are
designed to provide either bidirectional or unidirectional
buffer interface in Memory, Microprocessor, and Communi-
cation Systems. The output characteristics of the circuits
have low impedance sufficient to drive terminated trans-
mission lines down to 133鈩? The input characteristics of
the circuits likewise have a high impedance so it will not
significantly load the transmission line. The package con-
tains eight 3-STATE buffers organized with four buffers
having a common 3-STATE enable gate. The DM74AS240
and DM74AS244 are eight wide in a 20 pin package, and
may be used as a 4 wide bidirectional or eight wide unidi-
rectional. The buffer selection includes inverting and non-
inverting, with enable or disable 3-STATE control.
Features
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Improved switching performance with less power dissi-
pation compared with Schottky counterpart
s
Functional and pin compatible with 74LS and Schottky
counterpart
s
Switching response specified into 500鈩?and 50 pF
s
Specified to interface with CMOS at V
OH
=
V
CC
鈭?/div>
2V
Ordering Code:
Order Number
DM74AS240WM
DM74AS240N
DM74AS244WM
DM74AS244N
Package Number
M20B
N20A
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagrams
DM74AS240
DM74AS244
Function Tables
DM74AS240
Inputs
G
L
L
H
A
L
H
X
Output
Y
H
L
Z
H
=
HIGH Logic Level
DM74AS244
Inputs
G
L
L
H
X
=
Either LOW or HIGH Logic Level
Output
A
L
H
X
Y
L
H
Z
L
=
LOW Logic Level
Z
=
High Impedance
漏 2000 Fairchild Semiconductor Corporation
DS006298
www.fairchildsemi.com

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