54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders
June 1989
54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders
General Description
These BCD-to-decimal decoders consist of eight inverters
and ten four-input NAND gates The inverters are connect-
ed in pairs to make BCD input data available for decoding
by the NAND gates Full decoding of input logic ensures
that all outputs remain off for all invalid (10鈥?5) input condi-
tions
Features
Y
Y
Y
Y
Diode clamped inputs
Also for applications as 4-line-to-16-line decoders 3-
line-to-8-line decoders
All outputs are high for invalid input conditions
Alternate Military Aerospace device (54LS42) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram
Dual-In-Line Package
Function Table
No
0
1
2
3
4
5
6
7
8
9
I
N
V
A
L
I
D
BCD Inputs
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
0
L
H
H
H
H
1
H
L
H
H
H
2
Decimal Outputs
3
4
5
6
7
8
9
H H H H H H H H
H H H H H H H H
L H H H H H H H
H L H H H H H H
H H L H H H H H
H H H L H H H H
H H H H L H H H
H H H H H L H H
H H H H H H L H
H H H H H H H L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
TL F 6365 鈥?1
Order Number 54LS42DMQB 54LS42FMQB
DM54LS42J DM54LS42W DM74LS42M or DM74LS42N
See NS Package Number J16A M16A N16E or W16A
H
e
High Level
L
e
Low Level
Logic Diagram
TL F 6365 鈥?2
C
1995 National Semiconductor Corporation
TL F 6365
RRD-B30M105 Printed in U S A
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2
3
4
5
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