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EDX5116ABSE-3B-E Datasheet

  • EDX5116ABSE-3B-E

  • 512M bits XDR DRAM (32M words ?16 bits)

  • 3580.77KB

  • 78页

  • ELPIDA

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PRELIMINARY DATA SHEET
512M bits XDR
铮?/div>
DRAM
EDX5116ABSE (32M words
脳
16 bits)
Overview
The EDX5116ABSE is a 512M bits XDR
鈩?/div>
DRAM organized
as 32M words
脳
16 bits. It is a general-purpose high-perfor-
mance memory device suitable for use in a broad range of
applications.
The use of Differential Rambus Signaling Level (DRSL) tech-
nology permits 4000/3200/2400 Mb/s transfer rates while
using conventional system and board design technologies.
XDR DRAM devices are capable of sustained data transfers of
8000/6400/4800 MB/s.
XDR DRAM device architecture allows the highest sustained
bandwidth for multiple, interleaved randomly addressed mem-
ory transactions. The highly-efficient protocol yields over 95%
utilization while allowing fine access granularity. The device鈥檚
eight banks support up to four interleaved transactions.
It is packaged in 104-ball FBGA (
碌
BGA
餂?/div>
) compatible with
Rambus XDR DRAM pin configuration.
鈥?/div>
Low power
鈥?1.8V Vdd
鈥?Programmable small-swing I/O signaling (DRSL)
鈥?Low power PLL/DLL design
鈥?Powerdown self-refresh support
鈥?Per pin I/O powerdown for narrow-width operation
Pin Configuration
L
1
DQN3
DQN9
K
J
VDD
VDD
H
GND
G
VDD
F
Row
E
GND
D
VDD
C
SDI
GND
B
A
2
DQ3
1
2
3
4
5
6
7
DQN8 DQN2
DQ8
DQ2
DQ9
3
4
5
6
7
8
DQN15
DQ15
P
DQ5
DQN5
DQN5 VDD RQ10
CFM
RSRV
RSRV
VDD
DQN7 RQ0 DQN4
DQ7
RQ4
DQN14
VTERM GND
GND DQ4
RQ3
DQN3 VTERM VDD
DQ3
DQ14
VDD
GND
N
GND
VDD
DQ5 GND RQ11 CFMN
DQ1
DQN1
VDD VTERM
GND
GND
VDD
VDD
VREF
GND
VDD
VTERM
RQ10GND
RQ8
RQ6
RQ4
RQ2
RQ0 GND
VDD
GND
VDD
RQ7
RQ6
GND
GND
M
VDD
L
K
J
GND
VDD
RQ11
VDD
RQ9
RQ7
CFMN
RQ5
GND GND
VDD
GND
CFM
GND
Column
9
10
H
G
F
E
D
C
B
A
Features
鈥?/div>
Highest pin bandwidth available
4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling
鈥?Bi-directional differential RSL (DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
鈥?On-chip termination
-Adaptive impedance matching
-Reduced system cost and routing complexity
Highest sustained bandwidth per DRAM device
鈥?8000/6400/4800 MB/s sustained data rate
鈥?Eight banks: bank-interleaved transactions at full
bandwidth
鈥?Dynamic request scheduling
鈥?Early-read-after-write support for maximum efficiency
鈥?Zero overhead refresh
Dynamic width control
鈥DX5116ABSE supports
脳
16,
脳
8 and
脳
4 mode
Low latency
鈥?2.0/2.5/3.33 ns request packets
鈥?Point-to-point data interconnect for fastest possible
flight time
鈥?Support for low-latency, fast-cycle cores
11
12
13
14
15
16
GND
VDD
GND
RQ3
VDD
RQ1
VDD
VTERM GND
GND
GND
GND
VDD
GND
RST
GND GND
SD0
CMD
DQN13 VDD
RQ9
DQ0
DQN0
DQ13 CMD
RQ8
DQN7
DQ7
VREF
RQ5
SCK
RQ1
SD1
VDD DQN12 DQN6
DQ6
DQN2
DG2
RQ2
GND DQ12
VTERM
GND
VDD
DQN11 DQN1 SCK
DQ11
DQ4
DQN4
GND
DQ1
VDD
VDD
GND
GND
RST DQN0 DQN10
DQ10
DQN6
DQ6
VDD
SDO
DQ0
A16
A8
Top view of package
鈥?/div>
鈥?/div>
鈥?/div>
Doc. No. E0643E30 (Ver. 3.0)
Date Published August 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
铮?/div>
Elpida Memory, Inc.
2005

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