HDMP-0450 Datasheet

  • HDMP-0450

  • Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops

  • 272.69KB

  • 10页

  • AGILENT

扫码查看芯片数据手册

上传产品规格书

PDF预览

Agilent HDMP-0450
Quad Port Bypass Circuit
for Fibre Channel Arbitrated Loops
Data Sheet
Features
鈥?Supports 1.0625 GBd Fibre Channel
operation
Description
The HDMP-0450 is a Quad Port
Bypass Circuit (PBC) which
provides a low-cost, low-power
physical-layer solution for Fibre
Channel Arbitrated Loop (FC-AL)
disk array configurations. By using a
PBC such as the HDMP-0450, hard
disks may be pulled out or swapped
while other disks in the array are
available to the system.
A PBC consists of multiple 2:1
multiplexers daisy chained together.
Each port has two modes of
operation: 鈥渄isk in loop鈥?and 鈥渄isk
bypassed.鈥?When the 鈥渄isk in loop鈥?/div>
mode is selected, the loop goes into
and out of the disk drive at that
port. For example, data goes from
the HDMP-0450鈥檚 TO_NODE[n]卤
differential output pins to the Disk
Drive Transceiver IC鈥檚 (e.g., an
HDMP-1636A) Rx differential input
pins. Data from the Disk Drive
Transceiver IC鈥檚 Tx differential
outputs goes to the HDMP-0450鈥檚
FM_NODE[n]卤 differential input
pins. Figure 2 shows connection
diagrams for disk drive array
applications. When the 鈥渄isk
bypassed鈥?mode is selected, the
disk drive is either absent or
nonfunctional and the loop
bypasses the hard disk.
The 鈥渄isk bypassed鈥?mode is
enabled by pulling the BYPASS[n]-
pin low. Leave BYPASS[n]-
floating to enable the 鈥渄isk in
loop鈥?mode. HDMP-0450s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the appropriate
FM_NODE[n]卤 and
TO_NODE[n]卤 pins to
accommodate any number of hard
disks (see Figure 3). The unused
cells in the HDMP-0450 may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
An HDMP-0450 may also be
configured as five 1:1 buffers, as
two 2:1 multiplexers, or as two
1:2 buffers.
鈥?Supports 1.25 GBd Gigabit Ethernet
(GE) operation
鈥?Quad PBC in one package
鈥?Signal detect on FM_NODE[0] input
鈥?Equalizers on all inputs
鈥?High speed LVPECL I/O
鈥?Buffered Line Logic (BLL) outputs
(no external bias resistors required)
鈥?0.5 W typical power at V
CC
= 3.3 V
鈥?44 Pin, 10 mm, low-cost plastic QFP
package
Applications
鈥?RAID, JBOD, BTS cabinets
鈥?Two 2:1 muxes
鈥?Two 1:2 buffers
鈥?1 => N gigabit serial buffer
鈥?N => 1 gigabit serial mux
HDMP-0450
CAUTION:
As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling
and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic
discharge (ESD).

HDMP-0450相关型号PDF文件下载

  • 型号
    版本
    描述
    厂商
    下载
  • 英文版
    Optoelectronic
    ETC
  • 英文版
    Optoelectronic
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    1.0625-1.25 GBd Single Port Bypass Circuit wirh CDR for Fibr...
    ETC
  • 英文版
    Port Bypass Circuits for Fibre Channel Arbitrated Loop Stand...
    HP [Agilen...
  • 英文版
    Single Port Bypass Circuit with CDR & Data Valid Detection C...
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    AGILENT
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    AGILENT
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
    AGILENT
  • 英文版
    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
    HP [Agilen...
  • 英文版
    Octal Cell Port Bypass Circuit without Clock and Data Recove...
    AGILENT
  • 英文版
    Octal Cell Port Bypass Circuit without Clock and Data Recove...
    HP [Agilen...
  • 英文版
    Octal Cell Port Bypass Circuit with CDR and Data Valid Detec...
    HP [Agilen...
  • 英文版
    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA...
    ETC
  • 英文版
    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR A...
    ETC [ETC]
  • 英文版
    Receiver
    ETC

扫码下载APP,
一键连接广大的电子世界。

在线人工客服

买家服务:
卖家服务:

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号,
第一时间获取资讯。

建议反馈

联系人:

联系方式:

按住滑块,拖拽到最右边
>>
感谢您向阿库提出的宝贵意见,您的参与是维库提升服务的动力!意见一经采纳,将有感恩红包奉上哦!