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Single IC solution to existing designs requiring
multiple devices
Data and clock recovery for 125 MBaud FDDI or Fast
Ethernet applications
Clock multiplication from either a crystal, differential
or single-ended timing source
Continuous clock in the absence of data
No external PLL components
Lock/Loss status indicator output
Loopback mode for system diagnostics
Selectable loop timing mode
PECL driver with settable sink current
Parallel digital transmit and receive data interface
NRZ to/from NRZI data conversion
Consult ICS for optional configurations and data rates
Block Diagram
Pin Configuration
28-Pin SOIC
PHYceiver is a trademark of Integrated Circuit Systems, Inc.
ICS1887RevF112596