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ICS674R-01T Datasheet

  • ICS674R-01T

  • User Configurable Divider

  • 55.62KB

  • 6页

  • ICS

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PRELIMINARY INFORMATION
ICS674-01
User Configurable Divider
Description
The ICS674-01 consists of 2 separate
configurable dividers. The A Divider is a 7 bit
divider and can divide by 3 to 129. The
B Divider consists of a 9 bit divider followed by a
post divider. The 9 bit divider can divide by 12
to 519. The post divider has eight settings of
1, 2, 4, 5, 6, 7, 8 and 10 giving a maximum total
divide of 5190. The A and B Dividers can be
cascaded to give a maximum divide of 669510.
The ICS674-01 supports the ICS673 PLL
Building Block and enables the user to build a full
custom PLL synthesizer.
Features
鈥?Packaged as 28 pin SSOP (150 mil body)
鈥?Supports ICS673 PLL Building Block
鈥?User determines the divide by setting input pins
鈥?Pull-ups on all select inputs
鈥?Includes one 7-bit Divider for OUTA
鈥?Includes one 9-bit Divider and one selectable
Post Divider for OUTB
鈥?Operating voltages of 3.3 V or 5.0 V
鈥?Industrial temperature range available
鈥?25mA drive capability at TTL levels
鈥?Advanced, low power CMOS process
Block Diagram
A6:A0
7
VDD
2
GND
3
INA
Divider A
(7-Bit)
Output
Buffer
OUTA
INB
Divider B
(9-Bit)
Post
Divider
Output
Buffer
OUTB
9
B8:B0
3
S2:S0
1
Revision 033199
Printed 11/15/00
Integrated Circuit Systems 鈥?525 Race Street 鈥?San Jose 鈥?CA 鈥?95126 鈥?408)295-9800tel鈥?408)295-9818fax
MDS 674-01 A

ICS674R-01T 产品属性

  • Product Discontinuation 13/May/2009

  • 2,500

  • 集成电路 (IC)

  • 时钟/计时 - 时钟发生器，PLL，频率合成器

  • -

  • 时钟除法器

  • 无

  • 时钟

  • 时钟

  • 1

  • 2:2

  • 无/无

  • 235MHz

  • 是/无

  • 3 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面贴装

  • 28-SSOP（0.154"，3.90mm 宽）

  • 28-QSOP

  • 带卷 (TR)

  • 674R-01T

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