HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
x
x
IDT70V3379S
x
x
x
x
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
鈥?Commercial: 4.2/5/6ns (max.)
鈥?Industrial: 5/6ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
鈥?7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
鈥?Fast 4.2ns clock to data out
鈥?1.8ns setup to clock and 0.7ns hold on all control, data, and
x
x
x
x
x
address inputs @ 133MHz
鈥?Data input, address, byte enable and control registers
鈥?Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (卤150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (卤150mV)/2.5V (卤125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40掳C to +85掳C) is
available for selected speeds
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)
and 208-pin fine pitch Ball Grid Array, and 256-pin
Ball Grid Array
Functional Block Diagram
UB
L
LB
L
R/
W
L
B B
WW
0 1
L L
B B
WW
1 0
R R
UB
R
LB
R
R/
W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
32K x 18
MEMORY
ARRAY
I/O
0 L
- I/O
1 7 L
CLK
L
Din
_L
Din_R
I/O
0R
- I/O
17R
,.
CLK
R
A
14L
A
0L
CNTRST
L
ADS
L
CNTEN
L
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
14R
A
0R
CNTRST
R
ADS
R
CNTEN
R
4833 tbl 01
APRIL 2001
1
漏2001 Integrated Device Technology, Inc.
DSC 4833/8