IDT7133LA20JI Datasheet

  • IDT7133LA20JI

  • HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS

  • 141.81KB

  • 16页

  • IDT

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HIGH SPEED
2K X 16 DUAL-PORT
SRAM
Features
x
x
x
x
x
x
IDT7133SA/LA
IDT7143SA/LA
x
x
x
x
High-speed access
鈥?Military: 25/35/45/55/70/90ns (max.)
鈥?Industrial: 25/35/55ns (max.)
鈥?Commercial: 20/25/35/45/55/70/90ns (max.)
Low-power operation
鈥?IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
鈥?IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
Versatile control for write: separate write control for lower
and upper byte of each port
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
On-chip port arbitration logic (IDT7133 only)
x
x
BUSY
output flag on IDT7133;
BUSY
input on IDT7143
Fully asynchronous operation from either port
Battery backup operation鈥?V data retention
TTL-compatible; single 5V (卤10%) power supply
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (鈥?0掳C to +85掳C) is available
for selected speeds
Description
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.
The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port
RAM or as a 鈥淢ASTER鈥?Dual-Port RAM together with the IDT7143
鈥淪LAVE鈥?Dual-Port in 32-bit-or-more word width systems. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider
Functional Block Diagram
R/W
LUB
CE
L
R/W
RUB
CE
R
R/W
LLB
OE
L
R/W
RLB
OE
R
I/O
8L
- I/O
15L
I/O
0L
- I/O
7L
BUSY
L
(1)
A
10L
A
0L
ADDRESS
DECODER
11
I/O
CONTROL
I/O
CONTROL
I/O
8R
- I/O
15R
I/O
0R
- I/O
7R
BUSY
R
(1)
MEMORY
ARRAY
ADDRESS
DECODER
11
A
10R
A
0R
CE
L
ARBITRATION
LOGIC
(IDT7133 ONLY)
CE
R
2746 drw 01
NOTE:
1. IDT7133 (MASTER):
BUSY
is open drain output and requires pull-up resistor.
IDT7143 (SLAVE):
BUSY
is input.
JUNE 2000
1
漏2000 Integrated Device Technology, Inc.
DSC 2746/11

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