鈥?/div>
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
JTAG port, provided for Boundary Scan function (BGA Only)
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball
Grid Array (BGA) (with additional features)
Pin compatible to the SuperSync II (IDT72V223/72V233/72V243/
72V253/72V263/72V273/72V283/72V293) family
High-performance submicron CMOS technology
Industrial temperature range (鈥?0掳C to +85掳C) is available
掳
掳
FUNCTIONAL BLOCK DIAGRAM
*Available on the
BGA package only.
D
0
-D
n
(x9 or x18)
WEN
WCLK/WR
*
INPUT REGISTER
LD SEN
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
*
ASYW
WRITE CONTROL
LOGIC
FLAG
LOGIC
RAM ARRAY
131,072 x 18 or 262,144 x 9
262,144 x 18 or 524,288 x 9
WRITE POINTER
READ POINTER
BE
IP
IW
OW
MRS
PRS
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RM
ASYR
*
RCLK/RD
*
*
**
*
TCK
TRST
TMS
TDI
TDO
JTAG CONTROL
(BOUNDARY
SCAN)
*
OE
Q
0
-Q
n
(x9 or x18)
REN
*
6119 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
铮?/div>
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
SEPTEMBER 2003
DSC-6119/10
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