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IDT79RC32T355-150DH Datasheet

  • IDT79RC32T355-150DH

  • IDT Interprise Integrated Communications Processor

  • 991.93KB

  • 47页

  • IDT

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IDT
TM
Interprise
TM
Integrated
Communications Processor
79RC32355
Features List
RC32300 32-bit Microprocessor
鈥?Enhanced MIPS-II ISA
鈥?Enhanced MIPS-IV cache prefetch instruction
鈥?DSP Instructions
鈥?MMU with 16-entry TLB
鈥?8KB Instruction Cache, 2-way set associative
鈥?2KB Data Cache, 2-way set associative
鈥?Per line cache locking
鈥?Write-through and write-back cache management
鈥?Debug interface through the EJTAG port
鈥?Big or Little endian support
鈼?/div>
Interrupt Controller
鈥?Allows status of each interrupt to be read and masked
鈼?/div>
2
IC
鈥?Flexible I
2
C standard serial interface to connect to a variety of
peripherals
鈥?Standard and fast mode timing support
鈥?Configurable 7 or 10-bit addressable slave
鈼?/div>
UARTs
鈥?Two 16550 Compatible UARTs
鈥?Baud rate support up to 1.5 Mb/s
鈼?/div>
Counter/Timers
鈥?Three general purpose 32-bit counter/timers
鈼?/div>
General Purpose I/O Pins (GPIOP)
鈥?36 individually programmable pins
鈥?Each pin programmable as input, output, or alternate function
鈥?Input can be an interrupt or NMI source
鈥?Input can also be active high or active low
鈼?/div>
SDRAM Controller
鈥?2 memory banks, non-interleaved, 512 MB total
鈥?32-bit wide data path
鈥?Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
鈥?SODIMM support
鈥?Stays on page between transfers
鈥?Automatic refresh generation
鈼?/div>
Peripheral Device Controller
鈥?26-bit address bus
鈥?32-bit data bus with variable width support of 8-,16-, or 32-bits
鈥?8-bit boot ROM support
鈥?6 banks available, up to 64MB per bank
鈥?Supports Flash ROM, PROM, SRAM, dual-port memory, and
peripheral devices
鈥?Supports external wait-state generation, Intel or Motorola style
鈥?Write protect capability
鈥?Direct control of optional external data transceivers
鈼?/div>
System Integrity
鈥?Programmable system watchdog timer resets system on time-
out
鈥?Programmable bus transaction times memory and peripheral
transactions and generates a warm reset on time-out
鈼?/div>
DMA
鈥?16 DMA channels
鈥?Services on-chip and external peripherals
鈥?Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O
transfers
鈥?Supports flexible descriptor based operation and chaining via
linked lists of records (scatter / gather capability)
鈥?Supports unaligned transfers
鈥?Supports burst transfers
鈼?/div>
Block Diagram
RC32300
CPU Core
ICE
EJTAG
D. Cache
MMU
I. Cache
3 Counter
Timers
Watchdog
Timer
Interrupt
Controller
:
:
10/100
Ethernet
Interface
USB
Interface
16 Channel
DMA
Controller
Arbiter
Ext. Bus
Master
SDRAM &
Device
Controller
I
2
C
Controller
2 UARTS
(16550)
GPIO
Interface
TDM
Interface
ATM
Interface
Memory &
Peripheral Bus
I
2
C Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins
TDM Bus
Utopia 1 / 2
Figure 1 RC32355 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 47
漏
2004 Integrated Device Technology, Inc.
May 25, 2004
DSC 5900

IDT79RC32T355-150DH 产品属性

  • 24

  • 集成电路 (IC)

  • 嵌入式 - 微处理器

  • Interprise™

  • RISC 32-位

  • -

  • 150MHz

  • 2.5V

  • 表面贴装

  • 208-BFQFP

  • 208-PQFP（28x28）

  • 托盘

  • 79RC32T355-150DH

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