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IDT821034数据手册封面

IDT821034 Datasheet

  • IDT821034

  • QUAD PCM CODEC WITH PROGRAMMABLE GAIN

  • 306.83KB

  • IDT

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OCTAL E1 SHORT HAUL
LINE INTERFACE UNIT
FEATURES
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Fully integrated octal E1 short haul line interface which
supports 120鈩?E1 twisted pair and 75鈩?E1 coaxial appli-
cations
Selectable single rail or dual rail mode and AMI or HDB3
line encoder/decoder
Built-in transmit pre-equalization meets G.703
Selectable transmit/receive jitter attenuator meets ETSI
CTR12/13, ITU G.736, G.742 and G.823 specifications
SONET/SDH optimized jitter attenuator meets ITU G.783
mapping jitter specification
Digital/analog LOS detector meets ITU G.775 and ETS 300
233
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IDT82V2058
ITU G.772 non-intrusive monitoring for in-service testing
for any one of channel1 to channel7
Low impedance transmit drivers with tri-state
Selectable hardware and parallel/serial host interface
Local and remote loopback test functions
Hitless Protection Switching (HPS) for 1 to 1 protection
without relays
JTAG boundary scan for board test
3.3V supply with 5V tolerant I/O
Low power consumption
Operating temperature range: -40掳C to +85掳C
Available in 144-pin Thin Quad Flat Pack (TQFP_144_DA)
and 160-pin Plastic Ball Grid Array (PBGA) packages
FUNCTIONAL BLOCK DIAGRAM
LOS
Detector
RTIPn
RRINGn
Analog
Loopback
TTIPn
TRINGn
Peak
Detector
Line
Driver
Slicer
CLK&Data
Recovery
(DPLL)
Digital
Loopback
Waveform
Shaper
Transmit
All Ones
G.772
Monitor
Clock
Generator
One of Eight Identical Channels
LOSn
Jitter
Attenuator
HDB3/AMI
Decoder
Remote
Loopback
Jitter
Attenuator
HDB3/AMI
Encoder
AIS
Detector
RCLKn
RDn/RDPn
CVn/RDNn
TCLKn
TDn/TDPn
BPVIn/TDNn
Control Interface
Register
File
JTAG TAP
VDD IO
VDDT
VDDD
VDDA
OE
CLKE
MODE[2:0]
CS/JAS
SCLK/ALE/AS
RD/R/W
SDI/WR/DS
SD0/RDY/ACK
INT
LP/D/AD[7:0]
MC/A[4:0]
MCLK
Figure - 1. Block Diagram
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TRST
TCK
TMS
TDI
TDO
INDUSTRIAL TEMPERATURE RANGES
1
漏
2002 Integrated Device Technology, Inc.
JANUARY 2003
DSC-6038/9

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