鈥?Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and
AGP memory
鈥?One selectable frequency for VCH video channel clock
(48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)
鈥?Power management using power-down, CPU stop, and
PCI stop pins
鈥?Three function select pins (include test-mode select)
鈥?Cypress Spread Spectrum for best electromagnetic
interference (EMI) reduction
鈥?SMBUS support with readback
鈥?56-pin SSOP and TSSOP packages
Table 1. Function Table
[1]
TEST#
0
0
1
1
1
1
SEL1
X
X
0
0
1
1
SEL0
0
1
0
1
0
1
CPU(0:2)
Hi-Z
TCLK/2
66.6
100.0
133.3
133.3
SDRAM(0:5)
DCLK
Hi-Z
TCLK/2
100.0
[2]
3V66(0:2)
Hi-Z
TCLK/3
66.6
66.6
66.6
66.6
PCIF(1:6)
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
48M(0:1)
Hi-Z
TCLK/2
48
48
48
48
REF
Hi-Z
TCLK
14.318
14.318
14.318
14.318
IOAPIC(0:10)
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
100.0
[2]
133.3
100.0
[2]
Note:
1. These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices
SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.
2. Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
