data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized as follows.
IS42S83200B
54-pin TSOPII
IS42S16160B
54-pin TSOPII
54-ball BGA
8M x 8 x 4 Banks 4M x16x4 Banks
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS
Latency = 3
CAS
Latency = 2
Clk Frequency
CAS
Latency = 3
CAS
Latency = 2
Access Time from Clock
CAS
Latency = 3
CAS
Latency = 2
-6
6
8
166
125
5.4
6.5
-7
7
10
143
100
5.4
6.5
Unit
ns
ns
Mhz
Mhz
ns
ns
Copyright 漏 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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