IXF440 Datasheet

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IXF440 Multiport 10/100 Mbps Ethernet

Controller

Datasheet

Product Features

The IXF440 Multiport 10/100 Mbps Ethernet Controller (also called the

IXF440) provides eight 10/100 Mbps intelligent, high-performance MAC ports.

It includes network management support and is optimized for switch

applications.

s

Integration

鈥?Eight Ethernet 10/100 Mbps MAC ports

鈥?Onchip scrambler, descrambler, and PCS

functions for 100BASE-X connection

鈥?Handles SNMP and RMON counters

s

Operational

鈥?Enables independent 10 or 100 Mbps port

operation

鈥?Provides full-duplex support

鈥?Enables standard flow-control functionality in

full-duplex mode

鈥?Offers backpressure logic capability in

half-duplex mode

鈥?Interfaces to standard MII connections

鈥?Supports 10BASE-T, 100BASE-TX,

100BASE-T4, and 100BASE-FX connections

鈥?Provides programmable CRC generation and

removal

鈥?Allows backoff limit programming

鈥?Provides full collision support, including

jamming, backoff, and automatic

retransmission

鈥?Complies with IEEE 802.3 Standard

s

IX Bus

鈥?Supports a 4 Gbps high bus bandwidth

鈥?Variable bus speed of 25 to 66 MHz

operational, and from 16 MHz for testing

鈥?Interfaces a 64-bit bus with a 32-bit optional

mode

鈥?Supports concurrent unidirectional 32-bit

buses for transmit and receive in split IX Bus

mode

鈥?Provides transmit- and receive-independent

256-byte FIFOs for each of the eight ports

鈥?Offers a generic slave FIFO interface

鈥?Supports little or big endian byte ordering

鈥?Supports transmit and receive byte alignment

鈥?Supports receive packet fragmentation on byte

boundaries (replay feature)

鈥?Provides programmable transmit and receive

bus thresholds

鈥?Appends packet status to received packet

s

CPU Interface

鈥?Supports fully programmable independent

ports through a dedicated generic CPU port

鈥?Enables interrupt programming

s

Device

鈥?Optimized for switch, bridge, and router

applications

鈥?Includes internal and external loopback

capabilities

鈥?Provides software reset support

鈥?Supports JTAG boundary scan

鈥?Low-power 3.3 V and 5 V tolerant CMOS

device

鈥?352-BGA package

s

Performance

鈥?Allows status register access without

interrupting packet transfer

鈥?Enables early address filtering ability, with

packet header preprocessing and VLAN

detection ability

鈥?Offers retry or ignore options following

packet transmission errors

鈥?Supports automatic retransmission following

excessive collisions

鈥?Provides programmable automatic discard of

badly received packets such as runts, CRC

errors, and too long packets

Part Number: 278160-005

September, 2000

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